參數(shù)資料
型號(hào)： M38504M6A-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝： 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù)： 29/59頁(yè)
文件大?。?/td> 885K
代理商： M38504M6A-XXXFP
Rev.2.13
Apr 17, 2009
Page 35 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example,
because of a software run-away). The watchdog timer consists of
an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Initial value of watchdog timer
At reset or writing to the watchdog timer control register
(address 003916), each of watchdog timer H and L is set to
“FF16”. Any instruction which generates a write signal such as
the instructions of STA, LDM, CLB and others can be used to
write. The data of bits 6 and 7 are only valid when writing to the
watchdog timer control register. Each of watchdog timer is set to
“FF16” regardless of the written data of bits 0 to 5.
Bit 6 can be written to only once after reset release.
After this bit is written, it cannot rewritten because it is locked.
Operation of Watchdog Timer
The watchdog timer stops at reset and starts to count down by
writing to the watchdog timer control register. An internal reset
occurs at an underflow of the watchdog timer H. The reset is
released after waiting for a reset release time and the program is
processed from the reset vector address. Accordingly,
programming is usually performed so that writing to the
watchdog timer control register may be started before an
underflow. If writing to the watchdog timer control register is not
performed once, the watchdog timer does not function.
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the
MCU enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting (Note). When executing the WIT instruction, the
watchdog timer does not stop.
When bit 6 is “1”, execution of STP instruction causes an
internal reset. When this bit is set to “1” once, it cannot be
rewritten to “0” by program. Bit 6 is “0” at reset.
The required time after writing to the watchdog timer control
register to an underflow of the watchdog timer H is shown as
follows.
When bit 7 of the watchdog timer control register is “0”:
32 s at XCIN = 32.768 kHz frequency and
83.886ms at XIN = 12.5 MHz frequency.
When bit 7 of the watchdog timer control register is “1”:
125 ms at XCIN = 32.768 kHz frequency and
327.68
s at XIN = 12.5 MHz frequency.
Notes 1. The watchdog timer continues to count for waiting for a stop
mode release time. Do not generate an underflow of the watch-
dog timer H during that time.
2. The watchdog timer cannot be used in the middle-speed mode.
(The internal reset may not be generated correctly, depending on
the underflow timing of the watchdog timer.)
Fig 37. Block diagram of Watchdog timer
Fig 38. Structure of Watchdog timer control register
XIN
Data bus
XCIN
“10”
“00”
“01”
Main clock division
ratio selection bits (Note)
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction function selection bit
Watchdog timer H (8)
“FF16” is set when
watchdog timer
control register is
written to.
Internal reset
Watchdog timer L (8)
“FF16” is set when
watchdog timer
control register is
written to.
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
STP instruction
RESET
b7
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Watchdog timer control register
(WDTCON : address 003916)
b0
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