49
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
Fig. 54 Structure of MISRG
[MISRG (MISRG)] 0038
16
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to
“
1
”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to
“
1
”
, X
IN
oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
M
(
M
I
S
I
R
S
G
G
R
:
a
d
d
r
e
s
s
0
0
3
8
1
6
)
O
r
e
0
s
l
:
c
e
A
“
A
i
l
l
s
t
F
1
u
t
a
t
i
d
m
6
”
m
o
n
b
a
t
a
i
t
o
t
s
t
i
c
i
c
t
a
b
i
l
i
z
i
n
g
t
i
m
e
s
e
t
a
f
t
e
r
S
T
P
i
n
s
t
r
u
c
t
i
o
n
a
u
F
e
o
a
P
a
l
l
e
l
l
y
s
c
s
e
a
e
t
l
t
e
n
“
0
r
1
1
1
o
t
6
”
2
h
i
t
o
T
i
m
e
r
1
,
r
s
1
:
o
y
n
g
b
7
b
0
N
o
t
e
:W
t
c
h
e
h
e
m
a
n
n
d
e
t
h
d
s
e
l
e
.
-
m
s
o
p
d
e
e
i
s
m
a
o
u
d
t
e
o
,
m
t
a
e
t
i
v
c
a
a
l
u
l
y
e
s
o
w
f
i
t
c
P
h
U
e
d
m
f
o
r
d
o
m
e
e
t
h
g
e
i
s
t
l
e
o
w
r
-
a
s
d
p
d
e
r
e
e
d
s
m
0
o
0
d
3
e
B
1
t
o
6
h
i
e
d
h
l
C
r
(
s
g
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
M
(
D
0
1
i
d
e
I
A
d
p
n
l
e
v
u
e
-
s
d
i
d
m
p
i
n
e
g
e
d
o
n
m
o
p
d
o
e
g
r
a
a
u
m
t
o
)
m
a
t
i
c
s
w
i
t
c
h
s
t
a
r
t
b
i
t
n
l
o
r
:
:
a
t
a
t
i
c
s
w
i
t
c
h
s
t
a
r
t
M
0
1
i
d
4
6
d
.
.
l
e
-
t
t
s
o
o
p
5
7
e
.
.
e
5
5
d
m
m
m
a
a
o
c
c
d
h
h
e
n
n
e
e
a
u
c
c
t
y
y
o
c
c
m
l
e
l
e
a
s
s
t
i
c
s
w
i
t
c
h
w
a
i
t
t
i
m
e
s
e
t
b
i
t
:
:
5
5
i
i
M
0
1
i
d
N
A
d
o
u
l
e
t
t
o
-
s
m
s
e
p
t
a
e
a
t
e
u
i
c
d
t
o
s
m
m
w
o
a
i
t
d
t
c
e
i
c
h
a
i
n
a
u
l
l
g
t
o
m
a
t
i
c
s
w
i
t
c
h
s
e
t
b
i
t
:
:
y
e
n
a
b
l
e
W
I
T
i
n
s
t
r
u
c
t
i
o
n
STP instruction
T
i
m
i
n
g
φ
(
i
n
t
e
r
n
a
l
c
l
o
c
k
)
S
R
Q
S
T
P
i
n
s
t
r
u
c
t
i
o
n
S
R
Q
M
a
i
n
c
l
o
c
k
s
t
o
p
b
i
t
S
R
Q
1
/
2
1/4
X
IN
X
OUT
X
C
O
U
T
X
C
I
N
In
t
e
r
r
u
p
t
r
e
q
u
e
s
t
R
e
g
s
e
t
In
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
l
1
/
2
P
s
o
w
r
i
t
t
c
X
C
h
b
i
t
“
1
”
“
0
”
Low-speed mode
H
m
m
i
g
i
d
o
h
d
d
-
l
e
s
e
p
-
e
s
e
p
d
e
o
d
r
e
Middle-speed mode
High-speed or
low-speed mode
M
s
a
l
i
e
n
c
c
t
i
l
o
n
c
k
b
i
d
t
i
v
(
i
N
s
i
o
o
n
t
r
a
1
t
)
i
o
e
o
s
e
N
o
t
e
s
1
:
A
W
W
n
h
h
y
e
e
o
n
n
n
l
e
o
b
w
i
t
o
f
s
h
p
o
i
g
e
f
h
e
M
-
d
I
s
S
p
m
R
e
o
G
e
d
d
e
=
,
m
i
s
“
0
i
s
”
d
d
e
l
e
e
-
s
t
e
p
d
e
,
e
s
d
e
o
t
r
p
l
o
r
w
t
-
s
c
p
e
s
e
w
d
i
t
c
m
h
o
b
d
i
e
t
i
s
4
s
)
e
t
l
e
c
“
t
e
”
d
.
b
y
b
i
t
s
7
a
n
d
6
o
f
t
h
e
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
.
-
0
l
c
o
X
(
b
o
1
2
:
M
s
a
l
i
e
n
c
c
t
i
l
o
n
c
k
b
i
d
t
i
v
(
i
N
s
i
o
o
n
t
r
a
1
t
)
i
o
e
o
s
e
FF
16
01
16
P
r
e
s
c
a
l
e
r
1
2
Timer 1
Reset or
STP instruction
(Note 2)
R
e
s
e
t