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參數(shù)資料
| 型號(hào)： | M38507M8-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 91/99頁(yè) |
| 文件大?。?/td> | 1384K |
| 代理商： | M38507M8-XXXSP |
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91
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. A)
Timing requirements
Table 35 Timing requirements (1) (spec. A)
(V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, unless otherwise noted)
Reset input
“
L
”
pulse width
External clock input cycle time
External clock input
“
H
”
pulse width
External clock input
“
L
”
pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input
“
H
”
pulse width
CNTR
0
, CNTR
1
input
“
L
”
pulse width
INT
0
to INT
3
input
“
H
”
pulse width
INT
0
to INT
3
input
“
L
”
pulse width
Serial I/O1 clock input cycle time
(Note)
Serial I/O1 clock
input
“
H
”
pulse width
(Note)
Serial I/O1 clock
input
“
L
”
pulse width
(Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock
input
“
H
”
pulse width
Serial I/O2 clock
input
“
L
”
pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
Limits
Typ.
X
IN
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
20
80
32
32
200
80
80
80
80
800
370
370
220
100
1000
400
400
200
200
Max.
Symbol
Unit
Note :
When f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is
“
1
”
(clock synchronous).
Divide this value by four when f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is
“
0
”
(UART).
Table 36 Timing requirements (2) (spec. A)
(V
CC
= 2.7 to 5.5 V, V
SS
= 0 V, T
a
= –20 to 85 °C, unless otherwise noted)
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
x
D-S
CLK1
)
t
h
(S
CLK1
-R
x
D)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
IN2
-S
CLK2
)
t
h
(S
CLK2
-S
IN2
)
Reset input
“
L
”
pulse width
External clock input cycle time
External clock input
“
H
”
pulse width
External clock input
“
L
”
pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input
“
H
”
pulse width
CNTR
0
, CNTR
1
input
“
L
”
pulse width
INT
0
to INT
3
input
“
H
”
pulse width
INT
0
to INT
3
input
“
L
”
pulse width
Serial I/O1 clock input cycle time
(Note)
Serial I/O1 clock
input
“
H
”
pulse width
(Note)
Serial I/O1 clock
input
“
L
”
pulse width
(Note)
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock
input
“
H
”
pulse width
Serial I/O2 clock
input
“
L
”
pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR)
t
WH
(CNTR)
t
WL
(CNTR)
t
WH
(INT)
t
WL
(INT)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(R
x
D-S
CLK1
)
t
h
(S
CLK1
-R
x
D)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
IN2
-S
CLK2
)
t
h
(S
CLK2
-S
IN2
)
Limits
Typ.
X
IN
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
20
166
66
66
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
Max.
Symbol
Unit
Note :
When f(X
IN
) = 4 MHz and bit 6 of address 001A
16
is
“
1
”
(clock synchronous).
Divide this value by four when f(X
IN
) = 4 MHz and bit 6 of address 001A
16
is
“
0
”
(UART).
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