參數(shù)資料
型號(hào)： M3850
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁(yè)數(shù)： 36/51頁(yè)
文件大?。?/td> 736K
代理商： M3850
36
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 41 Structure of MISRG
[MISRG (MISRG)] 0038
16
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to “1”, X
IN
oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
Fig. 42 System clock generating circuit block diagram (Single-chip mode)
MISRG
(MISRG : address 0038
16
)
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “01
16
” to Timer 1,
“FF
16
” to Prescaler 12
1: Automatically set nothing
b7
b0
Note:the middle-speed mode, the value of CPU mode register (address 003B
16
)
changes.
Not used (return “0” when read)
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
WIT instruction
STP instruction
Timing f (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
S
R
Q
1/2
1/4
X
IN
X
OUT
X
COUT
X
CIN
Interrupt request
Reset
Interrupt disable flag l
1/2
Port X
C
switch bit
“1”
“0”
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits
(Note 1)
Notes 1:
Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b1) to “1”.
2:
When bit 0 of MISRG = “0”
Main clock division ratio
selection bits
(Note 1)
FF
16
01
16
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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