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參數(shù)資料
| 型號(hào)： | M3850B1 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 14/52頁(yè) |
| 文件大小： | 807K |
| 代理商： | M3850B1 |
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14
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 10 Interrupt control
Fig. 11 Structure of interrupt-related registers (1)
b7 b0
b7 b0
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
)
INT
0
active edge selection bit
INT
1
active edge selection bit
INT
2
active edge selection bit
INT
3
active edge selection bit
Reserved(Do not write “1” to this bit)
Not used (returns “0” when read)
Interrupt request register 1
(IREQ1 : address 003C
16
)
INT
interrupt request bit
Reserved
INT
1
interrupt request bit
INT
2
interrupt request bit
INT
3
interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
Interrupt control register 1
(ICON1 : address 003E
16
)
INT
0
interrupt enable bit
Reserved(Do not write "1" to this bit)
INT
1
interrupt enable bit
INT
2
interrupt enable bit
INT
3
interrupt enable bit
Reserved(Do not write "1" to this bit)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D
16
)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O reception interrupt request bit
Serial I/O transmit interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
Interrupt control register 2
(ICON2 : address 003F
16
)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O reception interrupt enable bit
Serial I/O transmit interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Falling edge active
1 : Rising edge active
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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