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參數(shù)資料
| 型號(hào)： | M38B79FFFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 37/109頁 |
| 文件大小： | 1559K |
| 代理商： | M38B79FFFP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
37
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 opera-
tion.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Fig. 37 Operation of clock synchronous serial I/O2 function
Fig. 36 Block diagram of clock synchronous serial I/O2
register (address 001D
16
) to
“
1
”
. For clock synchronous serial I/O,
the transmitter and the receiver must use the same clock for serial
I/O2 operation. If an internal clock is used, transmit/receive is
started by a write signal to the serial I/O2 transmit/receive buffer
register (TB/RB) (address 001F
16
).
When P6
7
(S
CLK22
) is selected as a clock I/O pin, S
RDY2
output
function is invalid, and P6
6
(S
CLK21
) is used as an I/O port.
1
/
4
1
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RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2
to
1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F
16
)
Notes1
: The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2
: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3
: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes
“
1
”
.
Receive enable signal
S
RDY2
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