參數(shù)資料
型號： M38C24M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 25/91頁
文件大?。?/td> 1867K
代理商： M38C24M4-XXXFP
30
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 24 Block diagram of Timer X, Y
Real time port
control bit
Real time port
control bit
Q D
Latch
Q D
Latch
P47 direction
register
P47 latch
P47 data for real time port
P46 direction
register
P46 latch
P46 data for real time port
“1”
Timer Y (low-order) latch (8)
“0”
CNTR1 active
edge switch bit
“10”
P47/RTP1/AN7
P46/RTP0/AN6
P60/CNTR1
Falling edge detection
Period measurement mode
Timer Y interrupt
request
Pulse width HL continuous
measurement mode
Timer Y operating
mode bits
CNTR1
interrupt request
Rising edge detection
Count source selection bit
XcIN
“1”
Clock for Timer Y
Data bus
1/2
1/4
Frequency
divider
Noise filter sampling
clock selection bit
“1”
“0”
Timer X interrupt
request
Equal
“000”
“001”
“010”
“011”
“101”
Pulse width
measurement mode
Timer X count
stop bit
Compare register (low-order)(8) Compare register (high-order)(8)
Output selection bit
P35 latch
P35
direction
register
P35/TXOUT/(LED5)
P51/INT1
P34/INT2/(LED4)
S
Q
T
R
TXOUT edge
switch bit
S
“0”
“1”
Q
T
S
Pulse output mode
CNTR0 active
edge switch bits
Timer X operating
mode bits
CNTR0
interrupt request
“100”
Extend latch (2)
Extend counter (2)
Timer X write
control bit
Timer 1 interrupt
D Q
Latch
Data for control of event counter window
P37/CNTR0/(LED7)
P50/INT0
0
s
Delay time
selection bits
4/f(XIN)
“00”
“01”
“10”
“11”
8/f(XIN)
16/f(XIN)
Noise filter
(4 times same
levels judgment)
INT0
interrupt request
Count source selection bit
XcIN
Clock for Timer X
System clock control bits
3
Clock for Timer Y
XIN
Real time port control bit
Timer Y mode register
write signal
Timer Y (low-order)(8)
XcIN
XIN
Frequency divider
IGBT output mode
PWM mode
Timer Y operating mode bits
Timer X frequency division
selection bit
Timer Y frequency division
selection bit
3
Both edges
detection
“00”
“01”
“10”
“11”
Edge
detection
TXOUT output
control bit 1
TXOUT output
control bit 2
Timer X
operating
mode bits
“010”
“00”, “01”, “11”
“1”
“0”
“1”
“0”
“1”
“0”
“00”, “01”, “10”
“11”
“0”
Timer Y write control bit
Timer Y count stop bit
“000”
“001”
“011”
“100”
“101”
Timer X operating
mode bits
“010”
Delay
circuit
Timer Y (high-order) latch (8)
Timer Y (high-order)(8)
Timer X (low-order) latch (8)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
Timer X (high-order)(8)
The following values can be selected
the clock for Timer;
1/1,1/2,1/16,1/32, 1/64,1/128,1/256,1/1024
“1”
“0”
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