參數(shù)資料
型號(hào)： M38C24M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 65/91頁
文件大?。?/td> 1867K
代理商： M38C24M4-XXXFP
5. Electrical Characteristics
Page 68 of 85
Figure 5.6
VCC1 = VCC2 = 5 V Timing Diagram (4/4)
BCLK
CSi
ADi
BHE
RD
ALE
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
td(AD-ALE)(1)
th(ALE-AD)(1)
tdz(RD-AD)
8ns.max
tac2(RD-DB)(1)
th(BCLK-CS)
-3ns.min
th(RD-DB) 0ns.min
th(BCLK-AD)
-3ns.min
td(BCLK-AD)
18ns.max
ADi /DBi
td(BCLK-RD)
18ns.max
tac2(AD-DB)(1)
th(BCLK-RD)
-5ns.min
th(RD-AD)(1)
tcyc
Address
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a
φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a
φ + bφ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a
φ + bφ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a
φ + bφ, p = {(a + b - 1) x 2} + 1)
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a
φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a
φ + bφ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 15) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a
φ + bφ, m = (b x 2) - 1)
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Address
VCC1=VCC2=5V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
Read Timing (2
φ + 2φ Bus Cycle)
tcyc=
109
f(BCLK)
BCLK
CSi
ADi
BHE
WR,WRL,WRH
Write Timing (2
φ + 2φ Bus Cycle)
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
td(AD-ALE)(2)
th(ALE-AD)(2)
td(DB-WR)(2)
th(WR-CS)(2)
td(BCLK-AD)
18ns.max
td(BCLK-WR)
18ns.max
th(BCLK-WR)
-5ns.min
tcyc
Address
Data output
th(WR-DB)(2)
ADi /DBi
ALE
Address
th(BCLK-AD)
-3ns.min
th(BCLK-CS)
-3ns.min
th(RD-CS)(1)
Data input
tsu(DB-BCLK) 26ns.min
th(WR-AD)(2)
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