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參數(shù)資料
| 型號： | M38C24M4-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 33/91頁 |
| 文件大?。?/td> | 1867K |
| 代理商： | M38C24M4-XXXHP |
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38
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Duty
ratio
2
3
4
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Bias Control and Applied Voltage to LCD Power
Input Pins
When the voltage is applied from the LCD power input pins (VL1–
VL3), set the VL pin input selection bit (bit 5 of the LCD power control
register) and VL3 connection bit (bit 6 of LCD power control register)
to “1”, apply the voltage value shown in Table 9 according to the bias
value. In this case, SEG22 pin and SEG23 pin cannot be used.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Fig. 34 Example of circuit at each bias (at external power input)
Table 9 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Note : VLCD is the maximum value of supplied voltage for the LCD panel.
Table 10 Duty ratio control and common pins used
Note: Unused common pin outputs the unselected waveform.
Common pins used
COM0, COM1
COM0–COM2
COM0–COM3
Bit 1
0
1
Bit 0
1
0
1
Duty ratio selection bit
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of
the LCD mode register). When reset is released, VCC voltage is out-
put from the common pin.
Segment Signal Output Pin
The segment signal output pins (SEG0–SEG23) are shared with ports
P0–P2. When these pins are used as the segment signal output pins,
set the direction registers of the corresponding pins to “1”, and clear
the segment output disable register to “0”.
Also, these pins are set to the input port after reset, the VCC voltage
is output by the pull-up resistor.
VL3
VL2
VL1
R4
R5
R4 = R5
Contrast adjust
1/2 bias
VL3
VL2
VL1
Contrast adjust
R1
R2
R3
R1 = R2 = R3
1/3 bias
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