參數(shù)資料
型號： M38C24M4-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 81/91頁
文件大?。?/td> 1867K
代理商： M38C24M4-XXXHP
5. Electrical Characteristics
Page 82 of 85
Figure 5.9
VCC1 = VCC2 = 3.3 V Timing Diagram (3/4)
VCC1=VCC2=3.3V
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a
φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a
φ + bφ, n = a + b)
Read Timing (1
φ + 1φ Bus Cycle)
Write Timing (1
φ + 1φ Bus Cycle)
NOTES:
3. Varies with operation frequency:
td(DB-WR) = (tcyc x m - 20) ns.min
(if external bus cycle a
φ + bφ, m = b)
th(WR-DB) = (tcyc / 2 - 20) ns.min
th(WR-AD) = (tcyc / 2 - 15) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
(if external bus cycle a
φ + bφ, n = (b x 2) - 1)
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
tcyc=
109
f(BCLK)
BCLK
CSi
ADi
BHE
DBi
th(BCLK-CS)
-3ns.min
td(BCLK-CS)
18ns.max
tcyc
td(BCLK-AD)
18ns.max
th(WR-AD)(3)
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
th(BCLK-AD)
-3ns.min
td(BCLK-WR)
18ns.max
tw(WR)(3)
th(WR-DB)(3)
th(WR-CS)(3)
WR,WRL,WRH
BCLK
CSi
ADi
BHE
RD
DBi
th(BCLK-CS)
-3ns.min
th(RD-CS)
0ns.min
td(BCLK-CS)
18ns.max(1)
tcyc
td(BCLK-AD)
18ns.max(1)
18ns.max
td(BCLK-RD)
th(RD-AD)
0ns.min
th(BCLK-RD)
-5ns.min
tac1(RD-DB)(2)
tac1(AD-DB)(2)
Hi-Z
th(RD-DB)
0ns.min
tsu(DB-BCLK)
30ns.min(1)
th(BCLK-AD)
-3ns.min
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