參數(shù)資料
型號: M38D24G4HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝: 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 91/136頁
文件大小: 2856K
代理商: M38D24G4HP
Rev.3.02
Apr 10, 2008
Page 58 of 131
REJ03B0177-0302
38D2 Group
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2
μs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC (min.)
and 5.5 V), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage
meets VIL spec. When a power source voltage passes VCC (min.).
In the flash memory version, input to the RESET pin in the
following procedure.
When power source is stabilized
(1) Input “L” level for 2
μs or more to RESET pin.
(2) Input “H” level to RESET pin.
At power-on
(1) Input “L” level to RESET pin.
(2) Increase the power source voltage to 2.7 V.
(3) Wait for td(P-R) until internal power source has stabilized.
(4) Input “H” level to RESET pin.
In the QzROM version, the input level applied to the OSCSEL
pin is determined when the RESET pin changes from “L” to “H”.
Fig. 56 Reset circuit example
Fig. 57 Reset sequence
VCC
Power source
voltage detection
circuit
RESET
VCC
RESET
0 V
VCC
RESET
0.2VCC or less
0 V
VCC
RESET
td(P-R) or more
5 V
2.7 V
(1)
Note 1: QzROM version: 2
μs or more
Flash memory version: td(P-R) or more
VCC (min.)
RESET
Internal
reset
Address
Data
SYNC
System clock
φ
OSCSEL=L: OCO
OSCSEL=H: XIN
FFFC
FFFD
ADH, ADL
ADL
ADH
????
Reset address from
vector table
OSCSEL=L: OCO= about 32768 cycles
OSCSEL=H: XIN= about 8192 cycles
Notes 1: The frequency of system clock
φ is f(OCO)/32 or f(XIN)/8.
2: The question marks (?) indicate an undefined state.
3: In the QzROM version, the input level applied to the OSCSEL pin is determined when the RESET pin changes from “L” to “H”.
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