參數(shù)資料
型號: M38D58G8HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 42/142頁
文件大小: 2004K
代理商: M38D58G8HP
(2/7)
REVISION HISTORY
38D5 Group Data Sheet
2.00
Jan 23, 2006
71
Table 14 Recommended operating conditions
- Vcc (Power source voltage) and Note revised.
- VIH, VIL (RESET) revised.
73
Table 16 Recommended operating conditions: all revised, Power source voltage
graph added.
74
Table 17 Electrical characteristics: ROSC
→ f(OCO)
75
Table 18 Electrical characteristics: Icc revised.
Table 19 A/D converter recommended operating condition revised.
76
Table 20 A/D converter characteristics: test conditions revised.
AD Power source voltage graph added.
77
Table 21 Timing requirements 1: tc(XIN), twH(XIN), twL(XIN) revised and Note added.
81
PACKAGE OUTLINE revised.
2.01
Mar 24, 2006
1
FEATURES: Power source voltage revised.
4
Performance overview: Oscillation frequency and Power source voltage revised.
17
Table 7 Related SFRs of port P7 revised.
52
Fig. 46: Address revised.
53
Fig. 50: Note 1 revised.
58
(1)Stop mode: Description revised.
59
Fig. 59
φSOURCE added.
60
Fig. 60 State transitions of system clock: Note 3 revised.
71
Table 14 : Vcc (Power source voltage) and Note 3 revised.
73
Table 16: Power source voltage (Main clock XIN frequency) graph added.
76
Table 20 Description of f(OCO) and Note revised.
2.02
Jul 10, 2006
15
Fig. 11: Register names of ROM correction addresses 1 and 2 revised.
22
Termination of unused pins
I/O ports : Description added.
23
Table 8
Termination 1 (recommended) : Delete (recommended).
Termination 1 to 3 of P70/C1/INT01 and P71/C2/INT11 : revised.
29
XCIN is selected as Timer 1, 2 count source : sentence is revised.
32
XCIN is selected as Timer X count source : sentence is revised.
33
Fig. 26: (TXCON1 bit 5 = “1”)
→(TXCON1 bit 5 = “0”)
35
XCIN is selected as Timer Y count source : sentence is revised.
43
Fig. 38: φSOURCE clock added.
52
Fig. 47: Border line in ROM area : revised.
53
Fig. 49: On chip oscillator
→ On chip oscillator/4
Fig. 50: b5 and b7 revised.
58
Frequency Control : Description added.
61
Table 12: Function of VREF and AVSS revised.
64 to 67
Fig. 63 to Fig. 66: Revised and added.
76
Table 17: Parameter of IIH and IIC added.
2.03
Aug 31, 2006
4
Table 1: Main clock and Sub-clock generating circuit : “feedback resistor”
eliminated.
7Table 3: AVSS : GND
→ Analog power source
23
Table 8: P41/TxD : input port
→ output port
P42/SCLK1 : output port
→ input port
Rev.
Date
Description
Page
Summary
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