參數(shù)資料
型號: M38D58G8HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 75/142頁
文件大?。?/td> 2004K
代理商: M38D58G8HP
Rev.3.04
May 20, 2008
Page 38 of 134
REJ03B0158-0304
38D5 Group
16-bit Timer
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write
the low-order byte first. The 16-bit timer cannot perform the
correct operation when reading during the write operation, or
when writing during the read operation.
Fig. 28 Timer X block diagram
Data bus
1/2
1/4
Frequency
divider
Noise filter sampling
clock selection bit
“1”
“0”
Timer X interrupt
request
Timer X (high-order)(8)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
Timer X (low-order) latch (8)
Equal
“000”
“001”
“010”
“011”
“101”
Pulse width
measurement
mode
Timer X count
stop bit
INT2
CNTR0 active
edge switch bits
Timer X operating
mode bits
CNTR0
interrupt request
“100”
Extend latch (2)
Timer X write
control bit
Timer 1 interrupt
D Q
Latch
Data for control of event counter window
CNTR0
INT00/INT01
0
s
External trigger delay time
selection bits
4/f(XIN)
“00”
“01”
“10”
“11”
8/f(XIN)
16/f(XIN)
Noise filter
(4 times same
levels judgment)
INT0
interrupt request
Timer X count source selection bit
XcIN
“1”
“0”
Clock for Timer X
XIN
Frequency divider
Timer X frequency
division selection bits
2
Both edges
detection
“00”
“01”
“10”
“11”
Timer X output
control bit 1
Timer X output
control bit 2
Timer X operating
mode bits
“010”
Delay
circuit
“000”
“001”
“011”
“100”
“101”
Timer X operating
mode bits
“010”
Compare register 3 (low-order)(8) Compare register 3 (high-order)(8)
Compare register 1 (low-order)(8) Compare register 1 (high-order)(8)
Compare register 2 (low-order)(8) Compare register 2 (high-order)(8)
Q
T
S
Pulse output mode
Timer X output 1
selection bit
P65
latch
P65
direction
register
P65/TXOUT1/(LED3)
Q
T
R
Timer X output 1
active edge switch
bit
“0”
“1”
IGBT output mode
PWM mode
Q
T
R
Timer X output 2
selection bit
P63
latch
P63
direction
register
P63/TXOUT2/(LED1)
Timer X output 2
active edge
switch bit
“0”
“1”
Extend counter (2)
φSOURCE
Note1:
φSOURCE indicates the followings:
XIN input in the frequency/2, 4, or 8 mode
On-chip oscillator divided by 4 in the on-chip oscillator mode
Sub-clock in the low-speed mode
“0”
“1”
Delay circuit 1/2
“1”
“0”
× 2
Trigger for IGBT input control bit
INT10/INT11
Edge
selection
Edge
selection
Edge
selection
Edge
detection
(1)
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