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參數(shù)資料
| 型號： | M38D59FFHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 93/142頁 |
| 文件大?。?/td> | 2004K |
| 代理商： | M38D59FFHP |
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Rev.3.04
May 20, 2008
REJ03B0158-0304
38D5 Group
Voltage Multiplier
The voltage multiplier performs threefold boosting. This circuit
inputs a reference voltage for boosting from LCD power input
pin VL1. Set each bit of the segment output disable registers and
the LCD mode registers in the following order for operating the
voltage multiplier.
(1) Set the segment output disable bits (bits 0 to 19) of the
segment output disable registers (SEG0, 1, 2) to “0” or “1”.
(2) Set the duty ratio selection bits (bits 0 to 2), the bias control
bit (bit 3), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register 1 to “0” or “1”.
(3) Set the VL3 connection bit (bit 1 of the LCD mode register 2
(LM2)) to “1”.
(4) Set the voltage multiplier control bit (bit0) of the LCD mode
register 2 to “1”.
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
The voltage multiplier is controlled by the voltage multiplier
control bit (bit 0 of the LCD mode register 2).
In addition, when the voltage multiplier is used, set the voltage
multiplier control bit to “1” (voltage multiplier enabled) after the
voltage 1.3 V or more and 2.1 V or less.
When the voltage multiplier is not used, set the VL3 connection
bit to “1” (open), and apply the suitable voltage for the power
supply input pins for LCD (VL1-VL3).
When VL3 connection bit is set to be open, VL3 pin is in a high
impedance state.
When the voltage multiplier is used, set the LCDCK frequency to
100 Hz or more. The on-chip oscillator cannot be used for
LCDCK.
In a system where the multiplier circuit is used (a multiplier
capacitor is externally connected between the C1 and C2 pins),
set the voltage multiplier circuit control bit to “1” (voltage
multiplier circuit enabled) before executing the STP or WIT
instruction.
Bias Control and Applied Voltage to LCD Power Input
Pins
Apply the voltage value shown in Table 13 according to the bias
value to the LCD power input pins. Apply the voltage value
shown in Table 13 according to the bias value by setting to VL3
connection bit (bit 1 of LCD mode register 1) to “1”, when the
voltage multiplier is not used.
Select a bias value by the bias control bit (bit 3 of the LCD mode
register 1).
NOTE:
1. VLCD is the maximum value of supplied voltage for the LCD
panel.
Common Pin and Duty Ratio Control
The common pins (COM0
COM7) to be used are determined by
duty ratio. Select duty ratio by the duty ratio selection bits (bits 0,
1 and 2 of the LCD mode register1). When reset is released, VCC
voltage is output from the common pin.
NOTE:
1. Unused common pin outputs the unselected waveform.
Segment Signal Output Pin
The segment signal output pins (SEG0
SEG31) are shared with
ports P0
P3. When these pins are used as the segment signal
output pins, set the direction registers of the corresponding pins
to “1”, and set the segment output disable register to “0”.
Also, these pins are set to the input port after reset, the VCC
voltage is output by the pull-up resistor.
Fig. 45 Example of circuit at each bias (at external power supply input)
Table 13
Bias control and applied voltage to VL1
VL3
Bias value
Voltage value
1/3 bias
VL3 = VLCD
VL2 = 2/3 VLCD
VL1 = 1/3 VLCD
1/2 bias
VL3 = VLCD
VL2 = VL1 = 1/2 VLCD
Table 14
Duty ratio control and common pins used
Duty
ratio
Duty ratio selection bits
Common pins used
Bit 2
Bit 1
Bit 0
10
0
COM0
20
0
1
COM0, COM1
30
1
0
COM0
COM2
40
1
COM0
COM3
81
1
COM0
COM7
R4
R5
R4 = R5
1/2 bias
Contrast adjust
R1
R2
R3
1/3 bias
Voltage multiplier is not used.
VL1
VL3
VL2
*
P71/INT11
P70/INT01
VL1
VL3
VL2
*
P71/INT11
P70/INT01
1/3 bias: R1 = R2 = R3
1/3 bias
Voltage multiplier is used.
VL1
VL3
VL2
C2
C1
1/1 bias (static)
VL1
VL3
VL2
Contrast adjust
* : When the voltage multiplier is not used, the C1 and C2 pins function as input ports P70/INT01, P71/INT11.
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