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參數(shù)資料
| 型號(hào)： | M391T2953CZ3-CCC |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 780K |
| 代理商： | M391T2953CZ3-CCC |
Rev. 1.5 October 2006
UDIMM
DDR2 SDRAM
20 of 24
Parameter
Symbol
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Note
min
max
min
max
min
max
min
max
DQ output access time from CK/CK
tAC
- 400
400
-450
+450
-500
+500
-600
+600
ps
DQS output access time from CK/CK
tDQSCK
- 350
350
-400
+400
-450
+450
-500
+500
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,t
CH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x
min(tCL,
tCH)
x
ps
Clock cycle time, CL=x
tCK
2500
8000
3000
8000
3750
8000
5000
8000
ps
DQ and DM input hold time
tDH(base)
125
x
175
x
225
x275
x
ps
DQ and DM input setup time
tDS(base)
50
x
100
x
100
x150
x
ps
Control & Address input pulse width for each
input
tIPW
0.6
x
0.6
x
0.6
x0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
x
0.35
x
0.35
x0.35
x
tCK
Data-out high-impedance time from CK/CK
tHZ
x
tAC max
x
tAC max
x
tAC max
x
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tAC
min
tAC max
2*tAC
min
tAC max 2* tACmin tAC max 2* tACmin
tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
x
200
x
240
x
300
x
350
ps
DQ hold skew factor
tQHS
x
300
x
340
x
400
x
450
ps
DQ/DQS output hold time from DQS
tQH
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
tHP -
tQHS
x
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH(base)
250
x
275
x375
x
475
x
ps
Address and control input setup time
tIS(base)
175
x
200
x250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page
size products
tRRD
7.5
x
7.5
x7.5
x
7.5
x
ns
Active to active command period for 2KB page
size products
tRRD
10
x
10
x10
x
10
x
ns
Four Activate Window for 1KB page size
products
tFAW
35
37.5
ns
Four Activate Window for 2KB page size
products
tFAW
45
50
ns
CAS to CAS command delay
tCCD
2
x
2
tCK
Write recovery time
tWR
15
x
15
x15
x
15
x
ns
Auto precharge write recovery + precharge time tDAL
WR+tRP
x
WR+tRP
x
WR+tRP
x
WR+tRP
x
tCK
Internal write to read command delay
tWTR
7.5
x7.5
x10
x
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
x200
200
tCK
Exit precharge power down to any non-read
command
tXP
2
x
2
x
2
x
2
x
tCK
14.3 Timing Parameters by Speed Grade
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| M391T2953CZ3-CD5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb C-die 64/72-bit Non-ECC/ECC |
| M391T2953CZ3-CE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb C-die 64/72-bit Non-ECC/ECC |
| M391T2953CZ3-CE600 | 制造商:Samsung Semiconductor 功能描述:512 DDR SDRAM MODUL X72 BOC(LF) - Trays |
| M391T2953CZ3-CE7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 512Mb C-die 64/72-bit Non-ECC/ECC |
| M391T3253FG0-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SDRAM MODULE |
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