參數(shù)資料
型號: M40Z111
廠商: 意法半導(dǎo)體
英文描述: NVRAM Controller for up to Two LPSRAM(NVRAM控制器)
中文描述: NVRAM中控制器最多兩個LPSRAM(NVRAM中控制器)
文件頁數(shù): 2/12頁
文件大小: 80K
代理商: M40Z111
AI02239
8
9
10
11
12
13
14
2
3
4
5
6
7
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
NC
NC
NC
NC
THS
VSS
NC
NC
NC
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E
NC
ECON
NC
NC
VOUT
VCC
M40Z111
M40Z111V
Figure 2. SOIC PinConnections
Warning:
NC = Not Connected.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
SNAPHAT
SOIC
–40 to 85
–55 to 125
°
C
T
SLD(2)
Lead Solder Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to V
CC
+0.3
V
V
CC
Supply Voltage
–0.3to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes:
1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied.Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negativeundershoots below –0.3volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wavesolder SOIC to avoid damaging SNAPHATsockets.
Table2. Absolute MaximumRatings
(1)
When an invalid V
CC
conditionoccurs, the condi-
tionedchipenable (E
CON
) outputis forced inactive
to write-protect the stored data in the SRAM.
Duringa powerfailure,the SRAMis switchedfrom
theV
CC
pin to the lithium cell withinthe SNAPHAT
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
writeprotecteduntilavalidpowerconditionreturns.
The28pin330milSOICprovidessocketswith gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
batterypackagetobe mountedon topof the SOIC
packageafter the completionof thesurfacemount
process. Insertion of the SNAPHAT housing after
reflowpreventspotentialbatterydamageduetothe
high temperatures required for device surface-
mounting.The SNAPHAThousingis keyedto pre-
vent reverse insertion. The SOIC and battery
packages are shipped separately in plastic anti-
statictubesor in Tape&Reelform.For the 28lead
SOIC, the battery package (i.e. SNAPHAT) part
number is ”M4Z28-BR00SH1” or ”M4Z32-
BR00SH1” (SeeTable 7).
OPERATION
The M40Z111/111W, as shown in Figure 4, can
control up to two standard low-power SRAMs.
TheseSRAMsmustbeconfiguredtohavethechip
enable input disable all other input signals. Most
slow, low-power SRAMs are configured like this,
howevermanyfast SRAMs arenot. Duringnormal
operating conditions, the conditionedchip enable
(E
CON
) output pin follows the chip enable (E) input
pinwithtimingshown in Table6. An internalswitch
connects V
CC
to V
OUT
. This switch has a voltage
drop of less than 0.3V (I
OUT1
).
DESCRIPTION
(cont’d)
2/12
M40Z111, M40Z111W
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