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參數(shù)資料
| 型號： | M41ST84 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5.0 OR 3.0V, 512 bit (64 x 8) Serial RTC with supervisory functions(具有監(jiān)控功能的5.0V或3.0V，512位(64 x 8)串行RTC) |
| 中文描述： | 5.0或3.0V，512位（64 × 8）（具有監(jiān)控功能的5.0V或3.0V，512位（64 × 8）串行時鐘監(jiān)督職能的串行時鐘） |
| 文件頁數(shù)： | 19/31頁 |
| 文件大?。?/td> | 181K |
| 代理商： | M41ST84 |
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19/31
M41ST84Y, M41ST84W
Figure 18. Back-Up Mode Alarm Waveform
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out intothe Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be themultiplica-
tion of the five-bit multiplier value with the resolu-
tion. (For example: writing 00001110 in the
Watchdog Register = 3*1, or 3 seconds).
Note:
Accuracy of timer is within
±
the selected
resolution.
If theprocessor does not reset the timer within the
specified period, the M41ST84Y/W sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ’0,’ the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a ’1,’the
watchdog will output a negative pulse on the RST
pin for t
REC
. The Watchdog register, FT,AFE, ABE
and SQWE Bits will reset to a ’0’ at the end of a
Watchdog time-out when the WDS Bit is set to a
’1.’
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note:
The WDI pin should be tied to V
SS
if not
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten
into
the
Watchdog
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a valueof
00h needs to be written to the Watchdog Register
in orderto clear the IRQ/FT/OUT pin. This willalso
disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the Frequency Test (FT)
function is activated, the watchdog function pre-
vails and the Frequency Test function is denied.
Register,
effectively
AI03920
VCC
VPFD
IRQ/FT/OUT
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
HIGH-Z
VSO
HIGH-Z
tREC
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| M41ST85WMX6E | 3.0/3.3V I2C Combination Serial RTC, NVRAM Supervisor and Microprocessor Supervisor |
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| M41ST95W | 5.0 or 3.0V, 512 bit (64 bit x8) Serial RTC (SPI) SRAM and NVRAM Supervisor(5.0/3.0V, 512位(64位x8)串行RTC(SPI) SRAM和NVRAM監(jiān)控電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST84W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84W_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.0/3.3 V I2C serial RTC with 44 bytes of NVRAM and supervisory functions |
| M41ST84WMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84WMH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
| M41ST84WMH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS |
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