參數(shù)資料
型號(hào): M41T00S
廠商: 意法半導(dǎo)體
英文描述: Serial Access Real-Time Clock(串行存取實(shí)時(shí)時(shí)鐘)
中文描述: 串行訪問(wèn)實(shí)時(shí)時(shí)鐘(串行存取實(shí)時(shí)時(shí)鐘)
文件頁(yè)數(shù): 10/23頁(yè)
文件大?。?/td> 319K
代理商: M41T00S
M41T00S
10/23
WRITE Mode
In this mode the master transmitter transmits to
the M41T00S slave receiver. Bus protocol is
shown in Figure
10
. Following the START condi-
tion and slave address, a logic '0' (R/W=0) is
placed on the bus and indicates to the addressed
device that word address “An” will follow and is to
be written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
see
Figure 7., page 8
and again after it has re-
ceived the word address and each data byte.
Data Retention Mode
With valid V
CC
applied, the M41T00S can be ac-
cessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the pow-
er input will be switched from the V
CC
pin to the
battery when V
CC
falls below the Battery Back-up
Switchover Voltage (V
SO
). At this time the clock
registers will be maintained by the attached bat-
tery supply. On power-up, when V
CC
returns to a
nominal value, write protection continues for t
REC
.
For a further, more detailed review of lifetime cal-
culations, please see Application Note AN1012.
Figure 10. WRITE Mode Sequence
AI00591
BUS ACTIVITY:
A
S
A
A
A
A
S
S
P
SDA LINE
BUS ACTIVITY:
MASTER
R
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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參數(shù)描述
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