參數(shù)資料
型號: M48T212V-85MH1F
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復及定時提取
英文描述: REAL TIME CLOCK, PDSO44
封裝: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44
文件頁數(shù): 4/35頁
文件大?。?/td> 348K
代理商: M48T212V-85MH1F
Obsolete
Product(s)
- Obsolete
Product(s)
Operation
M48T212V
Table 5.
Read mode AC characteristics
2.3
Write mode
The M48T212V is in the WRITE Mode whenever W (WRITE Enable) and E (Chip Enable)
are in a low state after the address inputs are stable. The start of a WRITE is referenced
from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid throughout the cycle. E or W must return
high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward.
G should be kept high during WRITE cycles to avoid bus contention; although, if the output
bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after
W falls.
When E is low during the WRITE, one of the on-board TIMEKEEPER registers will be
selected and data will be written into the device. When EX is low (and E is high) an external
SRAM location is selected.
Note:
Care should be taken to avoid taking both E and EX low simultaneously to avoid bus
contention.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).
M48T212V
Unit
–85
Min
Max
tAVAV
Read cycle time
85
ns
tAVQV
Address valid to output valid
85
ns
tELQV
Chip enable low to output valid
85
ns
tGLQV
Output enable low to output valid
35
ns
tELQX
(2)
2.
CL = 5pF.
Chip enable low to output transition
5
ns
tGLQX
Output enable low to output transition
0
ns
tEHQZ
Chip enable high to output Hi-Z
25
ns
tGHQZ
Output enable high to output Hi-Z
25
ns
tAXQX
Address transition to output transition
5
ns
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