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參數(shù)資料
| 型號： | M48T35AV-70PC6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 中文描述： | 256千位的32KB的SRAM x8計時器 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 148K |
| 代理商： | M48T35AV-70PC6 |
M48T35AY, M48T35AV
4/19
READ MODE
The M48T35AY/35AV is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
AVQV
) after the last address input signal is
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Access time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48T35AY/35AV is in the Write Mode when-
ever W and E are low. The start of a write is refer-
enced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of t
EHAX
from Chip Enable or t
WHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid t
DVWH
prior to the end of write and remain valid for t
WHDX
afterward. G should be kept high during write cy-
cles to avoid bus contention; although, if the output
bus has been activated by a low on E and G, a low
on W will disable the outputs t
WLQZ
after W falls.
Figure 3. Block Diagram
AI01623
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
32,760 x 8
SRAM ARRAY
A0-A14
DQ0-DQ7
E
W
G
POWER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T35AV-70PC6TR | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35AVPC | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35AVSH | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35AY | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35MH | 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T35AV-70PC6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM |
| M48T35AV-70PC6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM |
| M48T35AV-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T35AV-70PH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM |
| M48T35AV-70PH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V, 256 Kbit (32 Kb x8) TIMEKEEPER㈢ SRAM |
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