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參數(shù)資料
| 型號： | M48TMH1TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V PC REAL TIME CLOCK |
| 中文描述： | 5V的電腦實(shí)時(shí)時(shí)鐘 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 163K |
| 代理商： | M48TMH1TR |
M48T86
8/23
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70 °C)
Symbol
Parameter
Note: 1. All voltages referenced to V
SS
.
2.
At 25°C.
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C)
Note: 1. V
CC
fall time of less than t
F
may result in deselection/write protection not occurring until 200μs after V
CC
passes V
PFD
.
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
4.0
4.35
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR (2)
Expected Data Retention Time
10
YEARS
Symbol
Parameter
Min
Max
Unit
t
F
(1)
V
CC
Fall Time
300
μs
t
R
V
CC
Rise Time
100
μs
t
REC
V
PFD
to E High
20
200
ms
Figure 7. Power Down/Up Mode AC Waveforms
AI01646
VCC
4.5V
E
tF
tR
tREC
VPFD
VSO
INTERRUPTS
The RTC plus RAM includes three separate, fully
automatic sources of interrupt (alarm, periodic, up-
date-in-progress) available to a processor. The
alarm interrupt can be programmed to occur at
rates from once per second to once per day. The
periodic interrupt can be selected from rates of
500ms to 122μs. The update-ended interrupt can
be used to indicate that an update cycle has com-
pleted.
The processor program can select which inter-
rupts, if any, are going to be used. Three bits in
Register B enable the interrupts. Writing a logic "1"
to an interrupt-enable bit (Register B; Bit 6 = PIE;
Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be
initialized when the event occurs. A zero in an in-
terrupt-enable bit prohibits the IRQ pin from being
asserted from that interrupt condition. If an inter-
rupt flag is already set when an interrupt is en-
abled, IRQ is immediately set at an active level,
although the interrupt initiating the event may have
occurred much earlier. As a result, there are cases
where the program should clear such earlier initi-
ated interrupts before first enabling new interrupts.
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