參數(shù)資料
型號(hào)： M48TMH1TR
廠商： 意法半導(dǎo)體
英文描述： 5V PC REAL TIME CLOCK
中文描述： 5V的電腦實(shí)時(shí)時(shí)鐘
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 163K
代理商： M48TMH1TR
9/23
M48T86
Table 9. AC Characteristics
(T
A
= 0 to 70 °C; V
CC
= 4.5V to 5.5V)
Note: 1. See Table 10.
Symbol
Parameter
M48T86
Unit
Min
Typ
Max
t
CYC
Cycle Time
160
ns
t
DSL
Pulse Width, Data Strobe Low or R/W High
80
ns
t
DSH
Pulse Width, Data Strobe High or R/W Low
55
ns
t
RWH
R/W Hold Time
0
ns
t
RWS
R/W Setup Time
10
ns
t
CS
Chip Select Setup Time
5
ns
t
CH
Chip Select Hold Time
0
ns
t
DHR
Read Data Hold Time
0
25
ns
t
DHW
Write Data Hold Time
0
ns
t
AS
Address Setup Time
20
ns
t
AH
Address Hold Time
5
ns
t
DAS
Delay Time, Data Strobe to Address Strobe Rise
10
ns
t
ASW
Pulse Width Address Strobe High
30
ns
t
ASD
Delay Time, Address Strobe to Data Strobe Rise
35
ns
t
OD
Output Data Delay Time from Data Strobe Rise
50
ns
t
DW
Write Setup Time
30
ns
t
BUC
Delay Time before Update Cycle
244
μs
t
PI
(1)
Periodic Interrupt Time interval
–
–
–
t
UC
Time of Update Cycle
1
μs
When an interrupt event occurs, the related flag bit
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is
set to a logic "1". These flag bits are set indepen-
dent of the state of the corresponding enable bit in
Register B and can be used in a polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogate as necessary.
When a flag is set, an indication is given to soft-
ware that an interrupt event has occurred since the
flag bit was last read; however, care should be tak-
en when using the flag bits as all are cleared each
time Register C is read. Double latching is includ-
ed with Register C so that bits which are set, re-
main stable throughout the read cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the read
cycle are held until after the cycle is completed.
One, two, or three bits can be set when reading
Register C. Each utilized flag bit should be exam-
ined when read to ensure that no interrupts are
lost.
The second flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set
and the corresponding enable bit is also set, the
IRQ pin is asserted low. IRQ is asserted as long as
at least one of the three interrupt sources has its
flag and enable bits both set. The IRQF bit (Regis-
ter C; Bit 7) is a "1" whenever the IRQ pin is being
driven low. Determination that the RTC initiated an
interrupt is accomplished by reading Register C.A
logic "1" in the IRQF bit indicates that one or more
interrupts have been initiated by the M48T86. The
act of reading Register C clears all active flag bits
and the IRQF bit.
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