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參數(shù)資料
| 型號： | M48Z128CS |
| 廠商： | 意法半導體 |
| 英文描述： | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| 中文描述： | 1兆位的SRAM 128KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 106K |
| 代理商： | M48Z128CS |
3/17
M48Z128, M48Z128Y
Figure 3. Block Diagram
AI01196
INTERNAL
BATTERY
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x
8
SRAM ARRAY
A0-A16
DQ0-DQ7
W
G
POWER
E
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after thecompletion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the hightemperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Z28-BRxxSH1”.
The M48Z128/128Y also has its own Power-fail
Detect circuit. Thecontrol circuitry constantlymon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation broughton by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z128/128Y is in the Read Mode whenev-
er W (Write Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576locations in
the static storage array. Thus, the unique address
specified by the 17 Address Inputs defines which
one of the 131,072 bytesof data isto be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
isfied. If the Eand G access times are notmet, val-
id data will be available after the later of Chip
Enable Access time (t
ELQV
) or Output Enable Ac-
cess Time (t
GLQV
). The state of the eight three-
state Data I/O signals is controlled by E and G. If
the outputs are activated before t
AVQV
, the data
lines will be driven to an indeterminate state until
t
AVQV
. If the Address Inputs are changed while E
and G remain low, output data will remainvalid for
Output Data Hold time (t
AXQX
) but will go indeter-
minate until the next Address Access.
相關PDF資料 |
PDF描述 |
|---|---|
| M48Z128-85PM1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129V | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129V-70PM1 | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129V-85PM1 | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129VPM | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z128PM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128SH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER?? SRAM |
| M48Z128V-120PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM |
| M48Z128V-70PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 V or 3.3 V, 1 Mbit (128 Kbit x 8) ZEROPOWER? SRAM |
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