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參數(shù)資料
| 型號(hào)： | M48Z129V-85PM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| 中文描述： | 3.3V/5V的1兆位的SRAM 128KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 94K |
| 代理商： | M48Z129V-85PM1 |
1/13
June 2000
M48Z129Y
M48Z129V
3.3V/5V 1 Mbit (128Kb x8) ZEROPOWER
SRAM
I
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
I
AUTOMATIC POWER-FAIL CHIP DESELECT
AND WRITE PROTECTION
I
MICROPROCESSOR POWER-ON RESET
(RESET VALID EVEN DURING BATTERY
BACK-UP MODE)
I
BATTERY LOW PIN - PROVIDES WARNING
OF BATTERY END-OF-LIFE
I
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z129Y: 4.2V
≤
V
PFD
≤
4.5V
– M48Z129V: 2.7V
≤
V
PFD
≤
3.0V
I
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
I
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
I
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128Kb x 8 SRAMS
I
SELF CONTAINED BATTERY IN DIP
PACKAGE
Figure 1. Logic Diagram
AI02309
17
A0-A16
DQ0-DQ7
VCC
M48Z129Y
M48Z129V
G
VSS
8
E
W
RST
BL
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
RST
Reset Output (Open Drain)
BL
Battery Low Output (Open
Drain)
V
CC
Supply Voltage
V
SS
Ground
32
1
PMDIP32 (PM)
Module
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| M48Z129VPM | 3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z129V-85PM1 | 制造商:STMicroelectronics 功能描述:NVRAM 10 YR BATTERY 1MB 48Z129 |
| M48Z129V-85PMTR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM |
| M48Z129VPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V/5V 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z129Y_05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0V OR 3.3V, 1 Mbit (128 Kb x 8) ZEROPOWER SRAM |
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