參數(shù)資料
型號: M48Z128PM
廠商: 意法半導(dǎo)體
英文描述: 1 Mbit 128Kb x8 ZEROPOWER SRAM
中文描述: 1兆位的SRAM 128KB的x8 ZEROPOWER
文件頁數(shù): 2/17頁
文件大?。?/td> 106K
代理商: M48Z128PM
M48Z128, M48Z128Y
2/17
Figure 2. DIP Connections
A1
A0
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
A15
NC
DQ5
DQ4
DQ3
A16
A14
NC
VCC
AI01195
M48Z128
M48Z128Y
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A12
W
32
31
Table 2. Absolute Maximum Ratings
(1)
Symbol
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
–40 to 70
°
C
T
BIAS
Temperature Under Bias
–10 to 70
°
C
T
SLD(2)
Lead Solder Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
DESCRIPTION
The M48Z128/128Y ZEROPOWER
RAM is a
128 Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
ablein twospecial packagesto provide ahighly in-
tegrated battery backed-up memory solution.
The M48Z128/128Y is a non-volatile pin and func-
tion equivalent to any JEDEC standard 128K x8
SRAM. It also easily fits intomany ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number of writes
that can be performed. The 32 pin 600mil DIP
Module houses the M48Z128/128Y silicon with a
long life lithium button cell in a single package.
For surface mountenvironments STprovides a Chip
Set solution consisting of a 28 pin 330mil SOIC
NVRAM Supervisor (M40Z300) and a 32pin TSOP
(8x 20mm) LPSRAM (M68Z128) packages.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
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