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參數(shù)資料
| 型號(hào)： | M48Z30-85PM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CMOS 32K x 8 ZEROPOWER SRAM |
| 中文描述： | 的CMOS 32K的× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 100K |
| 代理商： | M48Z30-85PM1 |
Note:
Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to the absolute maximumratings conditions for extended periodsof time may affect reliability.
CAUTION:
Negatve undershootsbelow –0.3 volts are notallowed on any pin while in the Battery Back-up mode.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
–40 to 70
°
C
T
BIAS
Temperature Under Bias
–10 to 70
°
C
T
SLD
Lead Soldering Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
Table 2. Absolute MaximumRatings
Figure2. DIP Pin Connections
RAMdirectlyreplacesindustrystandardSRAMs. It
also fitsinto many EPROMandEEPROMsockets,
providing the nonvolatility of PROMs without any
requirement for special write timing or limitations
on the number of writes that can be performed.
The M48Z30/30Y has its own Power-fail Detect
Circuit.Thecontrolcircuitryconstantlymonitorsthe
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protectsthe SRAM,providingahighdegree ofdata
security in the midst of unpredictable system op-
erationsbrought on by low V
CC
. AsV
CC
fallsbelow
approximately3V, thecontrolcircuitry connectsthe
battery which sustains data until valid power re-
turns.
READ MODE
The M48Z30/30Y is in the Read Mode whenever
W(Write Enable)ishighandE(ChipEnable)islow.
The device architecture allows ripple-through ac-
cessof datafrom eight of 262,144locationsin the
static storage array. Thus, the unique address
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO
X
X
X
High Z
Battery Back-up Mode
Table 3. OperatingModes
Note
: X = V
IH
or V
IL
DESCRIPTION
(cont’d)
2/12
M48Z30, M48Z30Y
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| M48Z30PM | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30YPM | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z32V-35MT1TR | 3.3V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M48Z30PM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y-100PM1 | 制造商:STMicroelectronics 功能描述:NVRAM NVSRAM PARALLEL 256KBIT 5V 28PIN PMDIP - Bulk |
| M48Z30Y-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30YPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
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