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參數(shù)資料
| 型號： | M48Z32VMT |
| 廠商： | 意法半導體 |
| 英文描述： | 3.3V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM |
| 中文描述： | 3.3伏，256千位32千位× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 103K |
| 代理商： | M48Z32VMT |
M48Z32V
6/16
Table 5. DC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 3.0 to 3.6V (except where noted).
2. Outputs deselected.
3. Negative spikes of –1V allowed for up to 10ns once per cycle.
OPERATING MODES
The M48Z32V also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single power supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately V
SO
, the control circuitry con-
nects the battery which maintains data until valid
power returns.
Table 6. Operating Modes
Note: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
1. See Table 10, page 12 for details.
Sym
Parameter
Test Condition
(1)
Min
Typ
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±1
μA
I
LO(2)
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±1
μA
I
BAT
Battery Current
T
A
= 40°C; V
CC
= 0V
V
BAT
= 3V
0.2
1.2
μA
I
CC1
Supply Current
I
O
= 0mA; Cycle Time = Min
E = 0.2V, other input =
V
CC
– 2V or 0.2V
45
mA
I
CC2
Supply Current (TTL
Standby)
E = V
IH
800
μA
I
CC3
Supply Current (CMOS
Standby)
E = V
CC
– 0.2V
500
μA
V
IL(3)
Input Low Voltage
–0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= –1mA
0.8V
CC
V
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
3.0 to 3.6V
V
IH
X
X
High Z
Standby
WRITE
V
IL
X
V
IL
D
IN
Active
READ
V
IL
V
IL
V
IH
D
OUT
Active
READ
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(1)
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO(1)
X
X
X
High Z
Battery Back-up Mode
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