參數(shù)資料
型號: M48Z512A-70CS1
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8 ZEROPOWER SRAM
中文描述: 4兆位的SRAM 512KB的x8 ZEROPOWER
文件頁數(shù): 2/17頁
文件大?。?/td> 101K
代理商: M48Z512A-70CS1
M48Z512A, M48Z512AY
2/17
Figure 2. DIP Connections
A1
A0
DQ0
DQ1
DQ2
VSS
A7
A6
A5
A4
A3
A2
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
A15
A17
DQ5
DQ4
DQ3
A16
A14
A18
VCC
AI02044
M48Z512A
M48Z512AY
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A12
W
32
31
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
–40 to 70
°
C
T
BIAS
Temperature Under Bias
–40 to 70
°
C
T
SLD(2)
Lead Solder Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
DESCRIPTION
The M48Z512A/512AY ZEROPOWER
RAM is a
non-volatile 4,194,304 bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP Module.
For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300)and a 32 pin
TSOP Type II (10 x 20mm) LPSRAM (M68Z512)
packages.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of thesurface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the hightemperatures required for device surface-
mounting. The SNAPHAT housing is keyed topre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Zxx-BR00SH1”.
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M48Z58YSH Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Purple; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes
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