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參數(shù)資料
| 型號(hào)： | M48Z512A-70CS1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| 中文描述： | 4兆位的SRAM 512KB的x8 ZEROPOWER |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 101K |
| 代理商： | M48Z512A-70CS1 |
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M48Z512A, M48Z512AY
WRITE MODE
The M48Z512A/512AY is in the Write Mode when-
ever W and E are active. The start of a write is ref-
erenced from thelatter occurringfalling edge of W
or E.Awriteis terminatedby the earlier rising edge
of W or E.
The addresses must be held valid throughout the
cycle. Eor W must return high for a minimum of t
E-
Table 10. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. C
= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48Z512A/M48Z512AY
Unit
-70
-85
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
85
ns
t
AVWL
Address Validto Write Enable Low
0
0
ns
t
AVEL
Address Validto Chip Enable Low
0
0
ns
t
WLWH
Write Enable Pulse Width
55
65
ns
t
ELEH
Chip Enable Low to Chip EnableHigh
55
75
ns
t
WHAX
Write Enable High to Address Transition
5
5
ns
t
EHAX
Chip Enable High to Address Transition
15
15
ns
t
DVWH
Input Valid to WriteEnable High
30
35
ns
t
DVEH
Input Valid to Chip Enable High
30
35
ns
t
WHDX
Write Enable High to Input Transition
0
0
ns
t
EHDX
Chip Enable High to Input Transition
10
10
ns
t
WLQZ(1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
t
AVWH
Address Validto Write Enable High
65
75
ns
t
AVEH
Address Validto Chip Enable High
65
75
ns
t
WHQX(1, 2)
Write Enable High to Output Transition
5
5
ns
HAX
from E or t
WHAX
from W prior to the initiation
of another read or write cycle. Data-inmust be val-
id t
DVEH
or t
DVWH
prior to the end of write and re-
main valid for t
EHDX
or t
WHDX
afterward. G should
be kept high during write cycles to avoid bus con-
tention; although, if the output bus has been acti-
vated by a low on E and G, a low on W will disable
the outputs t
WLQZ
after W falls.
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| M48Z512AY | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512ASH | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512APM | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512ACS | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z58YSH | Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Purple; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z512A-70CS9 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512A-70PM1 | 功能描述:NVRAM 4M (512Kx8) 70ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| M48Z512A-70PM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER? SRAM |
| M48Z512A-70PM9 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512A-7-PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER SRAM |
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