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參數(shù)資料
| 型號(hào)： | M48Z512AY-70PM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| 中文描述： | 4兆位的SRAM 512KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 101K |
| 代理商： | M48Z512AY-70PM1 |
M48Z512A, M48Z512AY
6/17
Table 8. Power Down/Up AC Characteristics
(T
A
= 0 to 70
°
C)
Symbol
Note: 1. V
PFD
(max) to V
PFD
(min) falltime of less than t
F
may result indeselection/write protection not occurring until 200
μ
s after V
CC
pass-
es V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Parameter
Min
Max
Unit
t
F(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
μ
s
t
FB(2)
V
PFD
(min) to V
SO
V
CC
Fall Time
10
μ
s
t
WP
Write Protect Time from V
CC
= V
PFD
40
150
μ
s
t
R
V
SO
to V
PFD
(max) V
CC
Rise Time
0
μ
s
t
ER
E Recovery Time
40
120
ms
Figure 6. Power Down/Up Mode AC Waveforms
AI01031
VCC
VPFD(max)
E
(PER CONTROL INPUT)
OUTPUTS
DON’T CARE
HIGH-Z
tF
tFB
tR
tWP
tDR
VALID
VALID
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD(min)
VSO
tER
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| M48Z512AY-70PM1E | 制造商:STMicroelectronics 功能描述: |
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