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參數資料
| 型號： | M48Z512AY-70PM1 |
| 廠商： | 意法半導體 |
| 英文描述： | 4 Mbit 512Kb x8 ZEROPOWER SRAM |
| 中文描述： | 4兆位的SRAM 512KB的x8 ZEROPOWER |
| 文件頁數： | 8/17頁 |
| 文件大?。?/td> | 101K |
| 代理商： | M48Z512AY-70PM1 |
M48Z512A, M48Z512AY
8/17
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W) = High.
AI01221
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A18
E
G
DQ0-DQ7
VALID
READ MODE
The M48Z512A/512AY is in the Read Modewhen-
ever W (Write Enable) is high and E(Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 4,194,304 lo-
cations in the static storage array. Thus, the
unique addressspecifiedby the 19 Address Inputs
defines which one of the 524,288 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (t
AVQV
)
after thelast address inputsignal is stable, provid-
ing that the E (Chip Enable) and G (Output En-
able) access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the later of Chip Enable Access
time (t
ELQV
) or Output Enable Access Time
(t
GLQV
). The state of the eight three-state Data I/O
signals is controlled by E and G. If the outputs are
activated before t
AVQV
, the data lines will be driven
to an indeterminate state until t
AVQV
. If the Ad-
dress Inputs are changed while E and G remain
low, output data will remain valid for Output Data
Hold time (t
AXQX
) butwill go indeterminate until the
next Address Access.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M48Z512AY-70PM1E | 制造商:STMicroelectronics 功能描述: |
| M48Z512AY-70PM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER? SRAM |
| M48Z512AY-70PM9 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8 ZEROPOWER SRAM |
| M48Z512AY-7-PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER SRAM |
| M48Z512AY-7-PM6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit (512 Kbit x 8) ZEROPOWER SRAM |
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