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參數(shù)資料
| 型號(hào)： | M494 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SINGLE-CHIP VOLTAGE TUNING SYSTEM WITH 4 ANALOG CONTROLS AND mP INTERFACE |
| 中文描述： | 單片電壓調(diào)整系統(tǒng)，4模擬控制和MP接口 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 223K |
| 代理商： | M494 |
D
S
D
D0
D1
D2
D3
D4
DISPLAY
DRIVE
640
μ
s
(
2ms)
MUX PERIOD
(8ms)
I
4
Figure 5
FUNCTIONAL DESCRIPTION
(continued)
Display,Keyboard and Data Multiplexing
Logic is integratedon the chip to provide the mul-
tiplexing between the display, keyboard and data
inputs. In the On state and with the Data Hand-
shake pin at logic HI as an input the display and
keyboard are muxed together.See Figure 5. Each
column output goes to logic LO in sequence and
the row inputs are scanned for a key closure. In
chronological order across the total mux. period
there is : initialisation, scan, decision and display
periods.
The Data Handshake pin has a complex logical
function. It hastwo modes of operation: as a hand
shake I/O line to a
μ
P and as an output line to the
P to signalthat theM494is inthe Off state.In order
to achieve this function careful signal timing is
required both internally and externally to the chip.
See Figure6. Whenthe deviceis in the OFFstate
the Data Handshake pin is used to signal this
condition to the
μ
P by being pulled LO.
A1
B1
C1
D1
A2
B2
C2
D2
A3
DATA
DATA
O/I
I/O
O/I
I/O
(EOT = END OF
TRANSMISSION)
K/B AND RC I/P
DISABLEDTILL
EOT EXECYTION
DATA
HANDSHAKE
D0 - D4
EOE
(END OF TRANSMISSION)
NOT TO SCALE
DATA HANDSHAKE
PIN CONFIGURATION
t
RTS
t
CTS
t
O/P
t
H
t
CR
t
S
t
j
t
HS
t
CR
t
O/P
t
CTS
4
Figure 6 :
Data-input-timing
N
°
1
2
3
4
5
6
7
8
Symbol
t
RTS
t
CTS
t
O/P
t
HS
t
S
t
H
t
J
t
CR
Parameter
Min.
5
Typ.
Max.
10
Unit
μ
s
μ
s
ms
μ
s
μ
s
μ
s
ms
ms
Request to Send Pulse (RTS)
Clear to Send (CTS)
Pin Output Configuration
Handshake Time
Data Set up Time
Data Hold Time
Synchronization Jitter
CTS tonext RTS Pulse
512
8
12
10
128
128
256
8
98
Note :
Oscillator Clock = 500kHz
M494
7/22
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