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參數(shù)資料
| 型號(hào)： | M4A5-96/48-12VI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 15/62頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD ISP 4A 96MC 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispMACH® 4A |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 12.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 96 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
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ispMACH 4A Family
weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance
Characteristics on the Lattice Data Book CD-ROM or Lattice web site.
POWER MANAGEMENT
Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which
results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower
than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum
frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output
can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1
V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer
reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well
terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted
independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to
SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a
macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset,
then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be
monotonic, and the clock must be inactive until the reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the ispMACH 4A devices as a deterrent to unauthorized
copying of the array configuration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the
entire device.
HOT SOCKETING
ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot
socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and
inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH
devices be minimal on active signals.
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