M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 -5 -6 -7 -10 -12 -15 -20 Unit Min Max " />
參數(shù)資料
型號(hào): M5-384/160-12YI
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 16/42頁(yè)
文件大小: 0K
描述: IC CPLD ISP 384MC 160IO 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: MACH® 5
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 12.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
宏單元數(shù): 384
輸入/輸出數(shù): 160
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
MACH 5 Family
23
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Combinatorial Delay:
tPDi
Internal combinatorial propagation
delay
3.5
4.5
5.5
8.0
10.0
13.0
18.0
ns
tPD
Combinatorial propagation delay
5.5
6.5
7.5
10.0
12.0
15.0
20.0
ns
Registered Delays:
tSS
Synchronous clock setup time
3.0
4.0
5.0
6.0
8.0
10.0
ns
tSA
Asynchronous clock setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHS
Synchronous clock hold time
0.0
ns
tHA
Asynchronous clock hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tCOSi
Synchronous clock to internal output
2.5
3.0
4.0
5.0
6.0
8.0
10.0
ns
tCOS
Synchronous clock to output
4.5
5.0
6.0
7.0
8.0
10.0
12.0
ns
tCOAi
Asynchronous clock to internal output
6.0
8.0
10.0
13.0
15.0
18.0
ns
tCOA
Asynchronous clock to output
8.0
10.0
12.0
15.0
17.0
20.0
ns
Latched Delays:
tSAL
Latch setup time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tHAL
Latch hold time
3.0
4.0
5.0
6.0
7.0
8.0
ns
tPDLi
Transparent latch internal
6.0
7.0
8.0
9.0
10.0
ns
tPDL
Propagation delay through transparent
latch
8.0
9.0
10.0
11.0
12.0
ns
tGOAi
Gate to internal output
7.0
8.0
9.0
10.0
11.0
12.0
ns
tGOA
Gate to output
9.0
10.0
11.0
12.0
13.0
14.0
ns
Input Register Delays:
tSIRS
Input register setup time using a
synchronous clock
2.0
3.0
ns
tSIRA
Input register setup time using an
asynchronous clock
0.0
ns
tHIRS
Input register hold time using a
synchronous clock
3.0
4.0
ns
tHIRA
Input register hold time using an
asynchronous clock
6.0
7.0
ns
Input Latch Delays:
tSIL
Input latch setup time
2.0
3.0
ns
tHIL
Input latch hold time
6.0
7.0
ns
tPDILi
Transparent input latch
5.0
5.5
6.0
ns
Output Delays:
tBUF
Output buffer delay
2.0
ns
tSLW
Slow slew rate delay
2.5
ns
tEA
Output enable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
tER
Output disable time
7.5
9.5
10.0
12.0
15.0
20.0
ns
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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