參數(shù)資料
型號(hào)： M50FW080N5TP
廠商： 意法半導(dǎo)體
英文描述： 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器
文件頁(yè)數(shù)： 19/56頁(yè)
文件大?。?/td> 292K
代理商： M50FW080N5TP
M50FW080
Bus operations
19/55
3.2
Address/Address Multiplexed (A/A Mux) bus operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface.
The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash
Programming equipment for faster factory programming. Only a subset of the features
available to the Firmware Hub (FWH) Interface are available; these include all the
Commands but exclude the Security features and other registers.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are
unprotected. It is not possible to protect any blocks through this interface.
3.2.1
Bus Read
Bus Read operations are used to output the contents of the Memory Array, the Electronic
Signature and the Status Register. A valid Bus Read operation begins by latching the Row
Address and Column Address signals into the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP)
must be High, V
IH
, and Output Enable, G, Low, V
IL
, in order to perform a Bus Read
operation. The Data Inputs/Outputs will output the value, see
Figure 13
and
Table 24
, for
details of when the output becomes valid.
3.2.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
latching the Row Address and Column Address signals into the memory using the Address
Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, V
IH
and
Write Enable, W, must be Low, V
IL
. The Data Inputs/Outputs are latched on the rising edge
of Write Enable, W. See
Figure 14
and
Table 25
, for details of the timing requirements.
3.2.3
Output Disable
The data outputs are high-impedance when the Output Enable, G, is at V
IH
.
3.2.4
Reset
During Reset mode all internal circuits are switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is in Reset mode when RP is Low, V
IL
. RP
must be held Low, V
IL
for t
PLPH
. If RP is goes Low, V
IL
, during a Program or Erase operation,
the operation is aborted and the memory cells affected no longer contain valid data; the
memory can take up to t
PLRH
to abort a Program or Erase operation.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FW080NB1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1G 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1TG 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB5 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
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