參數(shù)資料
型號: M50LPW012K
廠商: 意法半導(dǎo)體
英文描述: 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述: 2兆位的256Kb × 8,啟動塊3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 13/35頁
文件大?。?/td> 239K
代理商: M50LPW012K
13/35
M50LPW012
During the polling period between issuing the
Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for
the operation to complete. Once Program/Erase
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended. For timing on the
delay between issuing the Program/Erase
Suspend command and the Program/Erase
Controller pausing see Table 13.
During Program/Erase Suspend the Read
Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume
commands will be accepted by the Command
Interface. Additionally, if the suspended operation
was Block Erase then the Program command will
also be accepted; only the blocks not being erased
may be read or programmed correctly.
See Figures 15, Program Suspend & Resume
Flowchart and Pseudo Code, and 18, Erase
Suspend & Resume Flowchart and Pseudo Code,
for suggested flowcharts on using the Program/
Erase Suspend command.
Program/Erase Resume Command.
The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
Pro-
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register can be read from
any address.
The Status Register bits are summarized in Table
14, Status Register Bits. Refer to Table 14 in con-
junction with the text descriptions below.
Program/Erase Controller Status (Bit 7).
The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inac-
tive.
The Program/Erase Controller Status is ‘0’ imme-
diately after a Program/Erase Suspend command
is issued until the Program/Erase Controller paus-
es. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Pro-
gram/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Pro-
gram/Erase Controller completes the operation
and the bit is ‘1’.
Table 13. Program and Erase Times
(T
A
= 0 to 70°C; V
CC
= 3.0 to 3.6V)
Note: 1. T
A
= 25°C, V
CC
= 3.3V
2. This time is obtained executing the Quadruple Byte Program Command.
3. Sampled only, not 100% tested.
4. 10
μ
s to program 4 Bytes.
Parameter
Interface
Test Condition
Min
Typ
(1)
Max
Unit
Byte Program
10
200
μ
s
Quadruple Byte Program
A/A Mux
V
PP
= 12V ± 5%
10
(4)
200
μ
s
Chip Erase
A/A Mux
V
PP
= 12V ± 5%
3
sec
Block Program (64 KBytes)
A/A Mux
V
PP
= 12V ± 5%
0.1
(2)
5
sec
V
PP
< 12V – 5%
0.4
5
sec
Block Erase (64 KBytes)
V
PP
= 12V ± 5%
0.75
8
sec
V
PP
< 12V – 5%
1
10
sec
Program/Erase Suspend to Program pause
(3)
5
μ
s
Program/Erase Suspend to Block Erase pause
(3)
30
μ
s
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