參數(shù)資料
型號: M51996AP
廠商: Mitsubishi Electric Corporation
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述: 抗輻射高效,5安培開關(guān)穩(wěn)壓器
文件頁數(shù): 20/22頁
文件大小: 366K
代理商: M51996AP
SWITCHING REGULATOR CONTROL
M51996AP/FP
MITSUBISHI (Dig./Ana. INTERFACE)
( 20
20
15
10
5
0
0
4
8
12
16
20
TOTAL STORED GATE CHARGE(nC)
Fig.35 The relation between applied gate-source
voltage and stored gate charge
I
D
=4A
As the gate drive current may reach up to several tenths
milliamperes at 500kHz operation,depending on the size of
MOS-FIT,the power dissipation caused by the gate current can
not be neglected.
In this case,following action will be considered to avoid heat
up of type M51996A.
(3)Output buffer circuit
It is recommended to use the output buffer circuit as shown in
Fig.36,when type M51996A drives the large capacitive load or
bipolar transistor.
1
2
3
V
DS
=80V
V
DS
=200V
V
DS
=320V
DRAIN
GATE
SOURCE
C
GS
C
GD
C
DS
V
GS
V
D
(1) To attach the heat sink to type M51996A
(2) To use the printed circuit board with the good
thermal conductivity
(3) To use the buffer circuit shown next section
M51996A
V
OUT
Fig.36 Output buffer circuit diagram
Fig.37 shows how to use the DET circuit for the voltage detector
and error amplifier.
For the phase shift compensation,it is recommended to
connected the CR network between det terminal and F/B
terminal.
DET
M51996A
Fig.37 How to use the DET circuit for the voltage
detector
C1
C
F/B
DET
C4
R2
B
R1
R3
C2
DETECTING
VOLTAGE
Fig.38 shows the gain-frequency characteristics between point
B and point C shown in Fig.37.
The G1, and are given by following equations;
2
R3
.............................................(10)
G1=
R1/R2
1
1
=
C2 R3
C1 + C2
2
=
C1 C2 R3
............................................(11)
....................................(12)
At the start of the operation,there happen to be no output pulse
due to F/B terminal current through C1 and C2,as the potential
of F/B terminal rises sharply just after the start of the operation.
Not to lack the output pulse,is recommended to connect the
capacitor C4 as shown by broken line.
Please take notice that the current flows through the R1 and R2
are superposed to Icc
(START)
.Not to superpose,R1 is connected
to Cvcc2 as shown in Fig.20.
G
AVDET
(DC VOLTAGE GAIN)
G1
1
2
Log
Fig.38 Gain-frequency characteristics between
point B and C shown in Fig.37
How to get the narrow pulse width during the
start of operation
Fig.39 shows how to get the narrow pulse width during the start
of the operation.If the pulse train of forcedly narrowed pulse-
width continues too long,the misstart of operation may
happen,so it is recommended to make the output pulse width
narrow only for a few pulse at the start of operation.0.1μF is
recommended for the C.
I
D
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