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參數(shù)資料
| 型號： | M52D32321A-7.5BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 32Bit x 2Banks Synchronous DRAM |
| 中文描述： | 1M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| 封裝： | 8 X 13 MM, LEAD FREE, VFBGA-90 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 707K |
| 代理商： | M52D32321A-7.5BG |
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ES MT
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
M52D32321A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.3
10/29
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence (decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
000
001
010
011
100
101
110
111
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx32 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M52S128168A | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-10BG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-10TG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-7.5BG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
| M52S128168A-7.5TG | 1M x 16 Bit x 4 Banks Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M52D32321A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32Bit x 2Banks Mobile Synchronous DRAM |
| M52D64164A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D64164A-10BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D64164A-10TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:1M x 16 Bit x 4 Banks Mobile Synchronous DRAM |
| M52D64322A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 32 Bit x 4 Banks Mobile Synchronous DRAM |
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