參數(shù)資料
型號: M52S32162A-7.5TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 2M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 16/30頁
文件大?。?/td> 787K
代理商: M52S32162A-7.5TG
ES MT
Page Read & Write Cycle at Same Bank @ Burst Length=4
M52S32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
1.2
16/30
*Note :
1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
CL=2
CL=3
WE
DQM
HIGH
t
RCD
*Note2
Ra
Ca0
Cb0
Cc0
Cd0
Ra
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd2
t
CDL
*Note1
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
DQ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
t
RDL
*Note3
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