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參數(shù)資料
| 型號(hào)： | M54HCT10 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TRIPLE 3-INPUT NAND GATE |
| 中文描述： | 三重3輸入與非門 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 232K |
| 代理商： | M54HCT10 |
M54HCT10
M74HCT10
February 1993
TRIPLE 3-INPUT NAND GATE
B1R
(Plastic Package)
ORDER CODES :
M54HCT10F1R
M74HCT10B1R
M74HCT10M1R
M74HCT10C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
t
PD
= 11 ns(TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 1
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS10
The M54/74HCT10 is a highspeed CMOS TRIPLE
3-INPUT NAND GATE fabricated with silicon gate
C
2
MOStechnology.Ithas thesame highspeedper-
formance of LSTTL combined with true CMOS low
power consumption. The internal circuit is com-
posedof 3 stages including bufferoutput, which en-
ables high noise immunity and stable output. All
inputs are equipped with protection circuits against
staticdischarge and transient excess voltage.
This integrated circuit has input and output charac-
teristics that are fully compatible with 54/74 LSTTL
logic families. M54/74HCT devices are designed to
directly interface HSC
2
MOS systems with TTL and
NMOS components. They are also plugin replace-
ments for LSTTL devices giving a reduction of
powerconsumption.
DESCRIPTION
1/9
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