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參數(shù)資料
| 型號(hào)： | M58BF008 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 256Kb x32, Burst Flash Memory |
| 中文描述： | 8兆位的256Kb X32號(hào)，突發(fā)快閃記憶體 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 231K |
| 代理商： | M58BF008 |
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M58BF008
18/36
Table 17. Synchronous Read AC Characteristics
(1)
(
T
A
= –40 to 125
°
C; V
DD
= 5V
±
10% and V
DDQ
= 3.3V
±
0.3V)
Symbol
Note: 1. See AC Testing Measurement Conditions for timing measurements.
2. Sampled only, not 100% tested.
Parameter
Min
Max
Unit
DC
CLK
System Clock Duty Cycle
45
55
%
t
AVCH(2)
Address Valid to System Clock High
10
ns
t
BALCH
Burst Address Advance Low to System Clock High
10
ns
t
BLCH(2)
Load Burst Address Low to System Clock High
10
ns
t
CHAX(2)
System Clock High to Address Transition
5
ns
t
CHBH(2)
System Clock High to Load Burst Address High
5
ns
t
CHCL
System Clock Fall Time
3
ns
t
CHGDH(2)
System Clock High to Output Disable High
5
ns
t
CHGH(2)
System Clock High to Output Enable High
5
ns
t
CHQV(2)
System Clock High to Data Valid
20
ns
t
CHQX1(2)
System Clock High to Data Transition
0
ns
t
CHQX2(2)
System Clock High to Data Transition
5
ns
t
CHQZ(2)
System Clock High to Data Hi-Z
20
ns
t
CLCH
System Clock Rise Time
3
ns
t
CLCL
System Clock Period
25
ns
t
ELCH
Chip Enable Low to System Clock High
20
ns
t
GDLCH(2)
Output Disable Low to System Clock High
10
ns
t
GLCH(2)
Output Enable Low to System Clock High
10
ns
t
PHBL
Reset/Power-down High to Load Burst Address Low
20
ns
t
WRHCH
Write/Read High to System Clock High
10
ns
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