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參數(shù)資料
| 型號： | M58BF008 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 256Kb x32, Burst Flash Memory |
| 中文描述： | 8兆位的256Kb X32號，突發(fā)快閃記憶體 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 231K |
| 代理商： | M58BF008 |
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M58BF008
DEVICE OPERATIONS
See Table 4 for Asynchronous or Synchronous
Bus Operations.
In theAsynchronous modethe memoryis selected
with Chip Enable E Low. The data outputs are en-
abled by Output Enable G Low or disabled by Out-
put DisableGD Low. Datais input byWrite Enable
W Low.
In the Synchronous mode thememory latches ad-
dresses and data (input or output) on the rising
edge of the System Clock CLK. Burst address
latching is enabled by Load Burst Address LBA
Low with Write/Read WR Low for a write cycle or
High for a read cycle.
Data outputs are enabled for reading on the rising
edge of the System Clock CLK when Output En-
able G is low. Data is input on the rising edge of
the System Clock CLK when Write Enable W is
Low.
The memory is deselected and in standby mode
when Chip Enable E is High, and it is reset or in
power-down mode when Reset/Power-Down RP
is Low.
Read.
Read operations are used to output the
contents of the memory, the Electronic Signature
or the Status Register. The data read depends on
the previous Instruction given to the memory.
Read operations can be Asynchronous or Syn-
chronous, witha single or burst read.On power-up
the device is in Asynchronous read mode, the In-
struction Asynchronous/Synchronous Read Tog-
gle ART can be used to enter the Synchronous
read mode.
– Asynchronous Read.
To read a data Double-
Word in Asynchronousmode the address inputs
must be stable and Chip Enable Emust be Low
during theread cycle. Output Enable Gmust be
Low and Output Disable GD High. The Load
Burst Address LBA is Don’t Care, but its falling
edge will start a new read cycle.
Table 4. Bus Operations
(1,2)
Note: 1. See Device Operations, Instructions and Commands, sections for more details.
2. X=V
IL
or V
IH.
Table 5. Read Electronic Signature
Note: ”x” = version level. The first version is ”0” and it can have a value up to ”7”.
Operation
RP
CLK
E
LBA
WR
W
GD
G
DQ0-DQ31
Asynchronous Read
V
IH
X
V
IL
X
X
V
IH
V
IH
V
IL
Data Output
Asynchronous Write
V
IH
X
V
IL
X
X
V
IL
V
IH
V
IH
Data Input
Synchronous Read
V
IH
V
IL
V
IH
V
IH
X
V
IH
V
IL
Data Output
Synchronous Write Address for
Read
V
IH
V
IL
V
IL
V
IH
X
V
IH
V
IH
X
Synchronous Write Address for
Command
V
IH
V
IL
V
IL
V
IL
X
V
IH
V
IH
X
Synchronous Data Write
V
IH
V
IL
V
IH
V
IH
V
IL
V
IH
V
IH
Data Input
Output Disabled by G
V
IH
X
V
IL
X
X
X
V
IH
V
IH
Hi-Z
Output Disabled by GD
V
IH
X
V
IL
X
X
X
V
IL
X
Hi-Z
Standby
V
IH
X
V
IH
X
X
X
X
X
Hi-Z
Reset / Power-down
V
IL
X
X
X
X
X
X
X
Hi-Z
Code
RP
E
G
W
A0
A1
A2-A17
DQ0-DQ31
Manufacturer
V
IH
V
IL
V
IL
V
IH
V
IL
V
IL
Don’t Care
00000020h
Device
V
IH
V
IL
V
IL
V
IH
V
IH
V
IL
Don’t Care
000000F0h
Version
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
Don’t Care
0000000xh
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