參數(shù)資料
型號: M58LW128B150N1T
廠商: 意法半導(dǎo)體
英文描述: RECEPTACLE HOUSING, 5WAY
中文描述: 128兆位和8Mb x16或4Mb的X32號,統(tǒng)一座,突發(fā)3V電源閃存
文件頁數(shù): 41/65頁
文件大?。?/td> 932K
代理商: M58LW128B150N1T
41/65
M58LW128A, M58LW128B
Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled
Symbol
Parameter
Test Condition
M58LW128
Unit
150
t
AVLH
Address Valid to Latch Enable High
Min
10
ns
t
AVEH
Address Valid to Chip Enable High
W = V
IL
Min
50
ns
t
DVEH
Data Input Valid to Chip Enable High
W = V
IL
Min
50
ns
t
WLEL
Write Enable Low to Chip Enable Low
Min
0
ns
t
WLLL
Write Enable Low to Latch Enable Low
Min
0
ns
t
LHAX
Latch Enable High to Address Transition
Min
3
ns
t
LHGL
Latch Enable High to Output Enable Low
Min
35
ns
t
LHEH
Latch Enable High to Chip Enable High
Min
0
ns
t
LLLH
Latch Enable low to Latch Enable High
Min
10
ns
t
LLEH
Latch Enable Low to Chip Enable High
Min
50
ns
t
VPHEH
Program/Erase Enable High to Chip Enable High
Min
0
ns
t
EHAX
Chip Enable High to Address Transition
W = V
IL
Min
10
ns
t
EHBL
Chip Enable High to Ready/Busy low
Max
90
ns
t
EHDX
Chip Enable High to Input Transition
W = V
IL
Min
10
ns
t
EHWH
Chip Enable High to Write Enable High
Min
0
ns
t
GHEL
Output Enable High to Chip Enable Low
Min
20
ns
t
EHGL
Chip Enable High to Output Enable Low
Min
35
ns
t
EHEL
Chip Enable High to Chip Enable Low
Min
30
ns
t
ELEH
Chip Enable Low to Chip Enable High
W = V
IL
Min
70
ns
t
ELLH
Chip Enable Low to Latch Enable High
W = V
IL
Min
10
ns
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