參數(shù)資料
型號(hào): M58LW128B150ZA6T
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
中文描述: 128兆位和8Mb x16或4Mb的X32號(hào),統(tǒng)一座,突發(fā)3V電源閃存
文件頁(yè)數(shù): 36/65頁(yè)
文件大?。?/td> 932K
代理商: M58LW128B150ZA6T
M58LW128A, M58LW128B
36/65
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms
Note: Asynchronous Read (M15 = 1), Latch Enable Controlled (M3 = 1)
Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics
Note: For other timings see Table 17, Asynchronous Bus Read Characteristics.
Symbol
Parameter
Test Condition
M58LW128
Unit
150
t
AVLL
Address Valid to Latch Enable Low
E = V
IL
Min
0
ns
t
AVLH
Address Valid to Latch Enable High
E = V
IL
Min
10
ns
t
LHLL
Latch Enable High to Latch Enable Low
Min
10
ns
t
LLLH
Latch Enable Low to Latch Enable High
E = V
IL
Min
10
ns
t
ELLL
Chip Enable Low to Latch Enable Low
Min
0
ns
t
ELLH
Chip Enable Low to Latch Enable High
Min
10
ns
t
LLQX
Latch Enable Low to Output Transition
E = V
IL
, G = V
IL
Min
0
ns
t
LLQV
Latch Enable Low to Output Valid
E = V
IL
, G = V
IL
Min
150
ns
t
LHAX
Latch Enable High to Address Transition
E = V
IL
Min
10
ns
t
GLQX
Output Enable Low to Output Transition
E = V
IL
Min
0
ns
t
GLQV
Output Enable Low to Output Valid
E = V
IL
Max
20
ns
t
EHLX
Chip Enable High to Latch Enable Transition
Min
0
ns
AI06132b
L
E
G
A1-A23
DQ0-DQx
VALID
tEHLX
tLHLL
tLHAX
tAVLL
tELLL
tLLLH
tELLH
tEHQX
tGHQZ
tGHQX
tLLQV
tGLQV
tGLQX
OUTPUT
tAVLH
tLLQX
tEHQZ
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