參數(shù)資料
型號： M58WR032F-ZBF
廠商： 意法半導(dǎo)體
英文描述： CAP 560PF 100V 1% NP0(C0G) AXIAL RAD.20 BULK R-MIL-PRF-20 STANDOFF
中文描述： 32兆位（含2Mb × 16，多銀行，突發(fā)）1.8V電源快閃記憶體
文件頁數(shù)： 26/86頁
文件大?。?/td> 1306K
代理商： M58WR032F-ZBF
M58WR032FT, M58WR032FB
26/86
CONFIGURATION REGISTER
The Configuration Register is used to configure
the type of bus access that the memory will per-
form. Refer to
READ MODES
section for details
on read operations.
The Configuration Register is set through the
Command Interface. After a Reset or Power-Up
the device is configured for asynchronous page
read (CR15 = 1). The Configuration Register bits
are described in
Table 9.
They specify the selec-
tion of the burst length, burst type, burst X latency
and the Read operation. Refer to Figures
6
and
7
for examples of synchronous burst configurations.
Read Select Bit (CR15)
The Read Select bit, CR15, is used to switch be-
tween asynchronous and synchronous Bus Read
operations. When the Read Select bit is set to ’1’,
read operations are asynchronous; when the
Read Select bit is set to ’0’, read operations are
synchronous. Synchronous Burst Read is support-
ed in both parameter and main blocks and can be
performed across banks.
On reset or power-up the Read Select bit is set
to’1’ for asynchronous access.
X-Latency Bits (CR13-CR11)
The X-Latency bits are used during Synchronous
Read operations to set the number of clock cycles
between the address being latched and the first
data becoming available. For correct operation the
X-Latency bits can only assume the values in
Ta-
ble 9., Configuration Register
.
The correspondence between X-Latency settings
and the maximum sustainable frequency must be
calculated taking into account some system pa-
rameters. Two conditions must be satisfied:
1.
Depending on whether t
AVK_CPU
or t
DELAY
is
supplied either one of the following two
equations must be satisfied:
(n + 1) t
K
≥
t
ACC
- t
AVK_CPU
+ t
QVK_CPU
(n + 2) t
K
≥
t
ACC
+ t
DELAY
+ t
QVK_CPU
2.
and also
t
K
> t
KQV
+ t
QVK_CPU
where
n is the chosen X-Latency configuration code
t
K
is the clock period
t
AVK_CPU
is clock to address valid, L Low, or E
Low, whichever occurs last
t
DELAY
is address valid, L Low, or E Low to clock,
whichever occurs last
t
QVK_CPU
is the data setup time required by the
system CPU,
t
KQV
is the clock to data valid time
t
ACC
is the random access time of the device.
Refer to
Figure 6., X-Latency and Data Output
Configuration Example
.
Wait Polarity Bit (CR10)
In synchronous burst mode the Wait signal indi-
cates whether the output data are valid or a WAIT
state must be inserted. The Wait Polarity bit is
used to set the polarity of the Wait signal. When
the Wait Polarity bit is set to ‘0’ the Wait signal is
active Low. When the Wait Polarity bit is set to ‘1’
the Wait signal is active High (default).
Data Output Configuration Bit (CR9)
The Data Output Configuration bit determines
whether the output remains valid for one or two
clock cycles. When the Data Output Configuration
Bit is ’0’ the output data is valid for one clock cycle,
when the Data Output Configuration Bit is ’1’ the
output data is valid for two clock cycles.
The Data Output Configuration depends on the
condition:
t
K
> t
KQV
+ t
QVK_CPU
where t
K
is the clock period, t
QVK_CPU
is the data
setup time required by the system CPU and t
KQV
is the clock to data valid time. If this condition is not
satisfied, the Data Output Configuration bit should
be set to ‘1’ (two clock cycles). Refer to
Figure 6.,
X-Latency and Data Output Configuration Exam-
ple
.
Wait Configuration Bit (CR8)
In burst mode the Wait bit controls the timing of the
Wait output pin, WAIT. When WAIT is asserted,
Data is Not Valid and when WAIT is deasserted,
Data is Valid. When the Wait bit is ’0’ the Wait out-
put pin is asserted during the wait state. When the
Wait bit is ’1’ (default) the Wait output pin is assert-
ed one clock cycle before the wait state.
Burst Type Bit (CR7)
The Burst Type bit is used to configure the se-
quence of addresses read as sequential or inter-
leaved. When the Burst Type bit is ’0’ the memory
outputs from interleaved addresses; when the
Burst Type bit is ’1’ (default) the memory outputs
from sequential addresses. See
Table 10., Burst
Type Definition
, for the sequence of addresses
output from a given starting address in each mode.
Valid Clock Edge Bit (CR6)
The Valid Clock Edge bit, CR6, is used to config-
ure the active edge of the Clock, K, during Syn-
chronous Burst Read operations. When the Valid
Clock Edge bit is ’0’ the falling edge of the Clock is
the active edge; when the Valid Clock Edge bit is
’1’ the rising edge of the Clock is active.
Wrap Burst Bit (CR3)
The burst reads can be confined inside the 4 or 8
Word boundary (wrap) or overcome the boundary
■
相關(guān)PDF資料
PDF描述
M58WR032F-ZBE 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR032F-ZBT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032KB70ZB6E 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 32Mbit 2M x 16bit 70ns 56-Pin VFBGA 制造商:Micron Technology Inc 功能描述:32M (X16) 1.8V, MULTIPLE BANK BURST, VFBGA56, IND, HAZMAT - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 32MBIT 70NS 56VFBGA
M58WR032KB70ZB6F 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel
M58WR032KB70ZB6F TR 制造商:Micron Technology Inc 功能描述:IC FLASH 32MBIT 70NS 56VFBGA
M58WR032KB70ZB6W 制造商:Micron Technology Inc 功能描述:2MX16 NOR FLASH PLASTIC PBF VFBGA 3.0V - Tape and Reel
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