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參數(shù)資料
| 型號： | M5913 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | COMBINED SINGLE CHIP PCM CODEC AND FILTER |
| 中文描述： | 組合單芯片的PCM編解碼器和過濾器 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 220K |
| 代理商： | M5913 |
AC CHARACTERISTICS - TIMING PARAMETERS
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
CLOCK SECTION
tCY
Clock Period, CLKX, CLKR
fCLKX =fCLKR = 2.048MHz
488
ns
tCLK
Clock Pulse Width
CLKX,CLKR
195
ns
tDCLK
Data Clock Pulse Width
1
64kHz
≤ fDCLK ≤ 2.048MHz
195
ns
tCDC
Clock Duty Cycle
CLKX,CLKR
40
50
60
%
tr,tf
Clock Rise and Fall Time
5
30
ns
TRANSMIT SECTION, FIXED DATA RATE MODE
2
tDZX
Data Enabled on TS Entry
0 < CLOAD < 100pF
0
145
ns
tDDX
Data Delay from CLKX
0< CLOAD < 100pF
0
145
ns
tHZX
Data Float on TS Exit
CLOAD = 0
60
190
ns
tSON
Timeslot X to Enable
0 < CLOAD < 100pF
0
145
ns
tSOFF
Timeslot X to Disable
CLOAD = 0
50
190
ns
tFSD
Frame Sync Delay
0
120
ns
tSS
Signal Setup Time
0
ns
tSH
Signal Setup Time
0
ns
RECEIVE SECTION, FIXED DATA RATE MODE
tDSR
Receive Data Setup
10
ns
tDHR
Receive Data Hold
60
ns
tFSD
Frame Sync Delay
0
120
ns
tSIGR
SIGR Update
0
2
s
TRANSMIT SECTION, FIXED DATA RATE MODE
2
tTSDX
Timeslot Delay from DCLKX
-80
80
ns
tFSD
Frame Sync Delay
0
120
ns
tDDX
Data Delay from DCLKX
0 < CLOAD < 100pF
0
100
ns
tDON
Timeslot to DX Active
0 < CLOAD < 100pF
0
50
ns
tDOFF
Timeslot to DX Inactive
0 < CLOAD < 100pF
0
80
ns
fDX
Data Clock Frequency
64
2048
1
KHz
tDFSX
Data Delay from FSX
tTSDX = 80ns
0
140
ns
RECEIVE SECTION, FIXED DATA RATE MODE
tTSDR
Timeslot Delay from DCLKR
-80
80
ns
tFSD
Frame Sync Delay
0
120
ns
tDSR
Receive Data Setup Time
10
ns
tDHR
Receive Data Hold Time
60
ns
tDR
Data Clock Frequency
64
2048
1
kHz
tSER
Timeslot End Receive Time
0
ns
64KB OPERATION, VARIABLE DATA RATE MODE
tFSLX
Transmit Frame Sync Minimum
Downtime
FSX is TTL high for
remainder of frame
488
ns
tFSLR
Receive Frame Sync Miniumum
Downtime
FSR is TTL high for
remainder of frame
1952
ns
tDCLK
Data Clock Pulse Width
10
s
Notes:
1. Devices are available wich operate at data rates up to 4.096MHz; the minimum data clock pulse width for these devices is 110ns
2. Timing parameters tDZX,tHZX, and tSOFF are referenced to a high impedance state.
M5913
13/17
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| M5913B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:COMBINED SINGLE CHIP PCM CODEC AND FILTER |
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| M5920025-AL | 制造商:OKW ENCLOSURES INC 功能描述:Enclosure;Cabinet;Rackmount;Aluminum;Gray;19In,2U,10.351InDepth;MettecSeries |
| M5920035-AL | 制造商:OKW ENCLOSURES INC 功能描述:Enclosure;Cabinet;Rackmount;Aluminum;Gray;19In,2U,14.469InDepth;MettecSeries |
| M5930025-AL | 制造商:OKW ENCLOSURES INC 功能描述:Enclosure;Cabinet;Rackmount;Aluminum;Gray;19In,3U,10.351InDepth;MettecSeries |
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