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參數(shù)資料
| 型號： | M59DR008EZB |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| 中文描述： | 8兆位512KB的x16插槽，雙行，第低壓閃存 |
| 文件頁數(shù)： | 21/37頁 |
| 文件大小： | 267K |
| 代理商： | M59DR008EZB |
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M59DR008E, M59DR008F
Table 25. Read AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; V
DD
= V
DDQ
= 1.65V to 2.2V)
Note: 1. Sampled only, not 100% tested.
2. G may be delayed by up to t
ELQV
- t
GLQV
after the falling edge of E without increasing t
ELQV
.
Symbol
Alt
Parameter
Test Condition
M59DR008
Unit
100
120
Min
Max
Min
Max
t
AVAV
t
RC
Address Valid to Next
Address Valid
E = V
IL
, G = V
IL
100
120
ns
t
AVQV
t
ACC
Address Valid to Output
Valid (Random)
E = V
IL
, G = V
IL
100
120
ns
t
AVQV1
t
PAGE
Address Valid to Output
Valid (Page)
E = V
IL
, G = V
IL
35
45
ns
t
ELQX
(1)
t
LZ
Chip Enable Low to Output
Transition
G = V
IL
0
0
ns
t
ELQV
(2)
t
CE
Chip Enable Low to Output
Valid
G = V
IL
100
120
ns
t
GLQX
(1)
t
OLZ
Output Enable Low to
Output Transition
E = V
IL
0
0
ns
t
GLQV
(2)
t
OE
Output Enable Low to
Output Valid
E = V
IL
25
35
ns
t
EHQX
t
OH
Chip Enable High to Output
Transition
G = V
IL
0
0
ns
t
EHQZ
(1)
t
HZ
Chip Enable High to Output
Hi-Z
G = V
IL
25
35
ns
t
GHQX
t
OH
Output Enable High to
Output Transition
E = V
IL
0
0
ns
t
GHQZ
(1)
t
DF
Output Enable High to
Output Hi-Z
E = V
IL
25
35
ns
t
AXQX
t
OH
Address Transition to
Output Transition
E = V
IL
, G = V
IL
0
0
ns
t
PHQ7V1
RP High to Data Valid
(Read Mode)
150
150
ns
t
PHQ7V2
RP High to Data Valid
(Power Down enabled)
50
50
μs
t
PLQ7V
RP Low to Reset Complete
During Program/Erase
15
μs
t
PLPH
t
RP
RP Pulse Width
100
100
ns
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