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參數(shù)資料
| 型號： | M5M44800CJ-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| 中文描述： | 快速頁面模式4194304位（524288 - Word的8位）動態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 202K |
| 代理商： | M5M44800CJ-6 |
FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM
M5M44800CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44800CJ,TP-5,-5S:Under development
Definition of RAS only distributed refresh
All combinations of nine row address signals (A
0
~A
9
) are
selected during 1024 constant period (16μs max.) RAS
only refresh cycles within 16.4ms.
Note 28:Self refresh sequence
Two refreshing methods should be used properly depending on the
low pulse width(t
RASS
) of RAS signal during self refresh period.
1. Distributed refresh during Read/Write operation
(A) Timing diagram
Read/Write Cycle
Self Refresh Cycle
Read/Write Cycle
t
NSD
t
RASS
≥
100μs
t
SND
last
refresh cycle
first
refresh cycle
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 1024
constant period (125μs max.) CBR cycles within 128ms.
The time interval t
NSD
from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh
operation should be set within 16μs.
Switching from self refresh operation to read/write operation.
The time interval t
SND
from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16μs.
RAS
(B) Definition of distributed refresh
RAS
t
REF
t
REF
/1024
refresh
cycle
read/write
cycles
t
REF
/
1024
read/write
cycles
refresh
cycle
refresh
cycle
20
Note: Switching from read/write operation to self refresh operation.
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within t
NSD
(shown in table 2).
1.1 CBR distributed refresh
1.2 RAS only distributed refresh
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end
of self refresh operation to the falling edge of RAS signal in the
first CBR refresh cycle during read/write operation period should
be set within t
SND
(shown in table 2)
Read/Write Cycle
CBR distributed
refresh
RAS only
distributed refresh
Read/Write
Self Refresh
Self Refresh
Read/Write
t
NSD
≤
16μs
t
SND
≤
16μs
t
NSD
≤
125μs
t
SND
≤
125μs
Table 2
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參數(shù)描述 |
|---|---|
| M5M44800CJ-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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| M5M44800CJ-7S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CTP-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
| M5M44800CTP-5S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (524288-WORD BY 8-BIT) DYNAMIC RAM |
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