參數(shù)資料
型號: M5M4V16G50DFP-10
廠商: Mitsubishi Electric Corporation
英文描述: 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
中文描述: 1,600(2 -銀行甲262144字× 32位)同步圖形RAM
文件頁數(shù): 18/33頁
文件大?。?/td> 167K
代理商: M5M4V16G50DFP-10
M5M4V16G50DFP -8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0)
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SGRAM has two independent banks. Each bank is activated by the ACT command with the bank
address (A10/BA). A row is indicated by the row address A9-0. The minimum activation interval between
one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by A10/BA. When both banks are active, the
precharge all command (PREA, PRE + A9=H) is available to deactivate them at the same time. After tRP
from the precharge, an ACT command can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after
the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The
start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A
READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind
continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a READ
command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the
same bank is inhibited until the internal precharge is complete. The internal precharge start timing depends on
/CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing.
Bank Activation and Precharge All (BL=4, CL=3)
CLK
Command
A0-8
A9
A10
DQ
ACT
Xa
Xa
0
READ
Y
0
0
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
1
PRE
tRRD
tRCD
1
ACT
Xb
Xb
1
Precharge all
tRAS
tRP
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