參數(shù)資料
型號： M5M4V64S20ATP-8A
廠商： Mitsubishi Electric Corporation
英文描述： 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
中文描述： 64M號（4銀行甲4194304字× 4位）同步DRAM
文件頁數(shù)： 18/48頁
文件大?。?/td> 1097K
代理商： M5M4V64S20ATP-8A
M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of
the same bank
. READ to PRE interval is mini-
mum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result,
READ to PRE interval determines valid data length to be output. The figure below shows examples of
BL=4.
Read Interrupted by Precharge (BL=4)
CLK
CL=3
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
CL=2
Command
DQ
READ
PRE
Q0
Q1
Q2
Command
DQ
READ
PRE
Q0
Command
DQ
READ PRE
Q0
Q1
Command
DQ
READ PRE
Q0
Q1
18
相關(guān)PDF資料
PDF描述
M5M4V64S20ATP-8L 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M51008KR-10L 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M51008KR-10LL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M51008KR-55L 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
M5M51008KR-55LL 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M4V64S20ATP-8L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
M5M4V64S30ATP-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-10L 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-12 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
M5M4V64S30ATP-8 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
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